Block diagram. Infineon CY8C4045LQI-S412, CY8C4045LQI-S413, CY8C4025AZI-S413T, CY8C4024LQI-S412, CY8C4025AZQ-S403, CY8C4024LQI-S403T, CY8C4025LQI-S412, CY8C4025LQI-S402T, CY8C4045LQI-S411, CY8C4024AXI-S412

PSoC™ 4 MCU: PSoC™ 4000S

Based on Arm® Cortex®-M0+ CPU

Block diagram

Block diagram

PSoC™ 4000S

Architecture

32-bit

AHB-Lite

System Resources

Lite

Power

Sleep Control

WIC

POR

PWRSYS

REF

Clock

Clock Control

WDT

ILO IMO

Reset

Reset Control

XRES

Test

TestMode Entry

Digital DFT

Analog DFT

CPU Subsystem

SWD/TC

Cortex® M0+

48 MHz

FAST MUL

NVIC, IRQMUX

SPCIF

FLASH

32 KB

Read Accelerator

SRAM

4 KB

SRAM Controller

Peripherals

PCLK

System Interconnect (Single Layer AHB)

Peripheral Interconnect (MMIO)

ROM

8 KB

ROM Controller

Power Modes

Active/Sleep

DeepSleep

High Speed I/O Matrix & 2 x Programmable I/O

36x GPIOs, LCD

I/O Subsystem

PSoC™ 4000S devices include extensive support for programming, testing, debugging, and tracing both hardware and firmware.

The Arm® serial-wire debug (SWD) interface supports all programming and debug features of the device.

Complete debug-on-chip functionality enables full-device debugging in the final system using the standard production device. It does not require special interfaces, debugging pods, simulators, or emulators. Only the standard programming connections are required to fully support debug.

The PSoC™ Creator IDE provides fully integrated programming and debug support for the PSoC™ 4000S devices.

The SWD interface is fully compatible with industry-standard third-party tools. The PSoC™ 4000S provides a level of security not possible with multi-chip application solutions or with microcontrollers.

It has the following advantages:

• Allows disabling of debug features

• Robust flash protection

• Allows customer-proprietary functionality to be implemented in on-chip programmable blocks

Datasheet 7 002-00123 Rev. *O

2022-07-28

PSoC™ 4 MCU: PSoC™ 4000S

Based on Arm® Cortex®-M0+ CPU

Block diagram

The debug circuits are enabled by default and can be disabled in firmware. If they are not enabled, the only way to re-enable them is to erase the entire device, clear flash protection, and reprogram the device with new firmware that enables debugging. Thus firmware control of debugging cannot be over-ridden without erasing the firmware thus providing security.

Additionally, all device interfaces can be permanently disabled (device security) for applications concerned about phishing attacks due to a maliciously reprogrammed device or attempts to defeat security by starting and interrupting flash programming sequences. All programming, debug, and test interfaces are disabled when maximum device security is enabled. Therefore, PSoC™ 4000S, with device security enabled, may not be returned for failure analysis. This is a trade-off the PSoC™ 4000S allows the customer to make.

Datasheet 8 002-00123 Rev. *O

2022-07-28