4.1 Alternate pin functions. Infineon CY8C4045LQI-S412, CY8C4045LQI-S413, CY8C4025AZI-S413T, CY8C4024LQI-S412, CY8C4025AZQ-S403, CY8C4024LQI-S403T, CY8C4025LQI-S412, CY8C4025LQI-S402T, CY8C4045LQI-S411, CY8C4024AXI-S412

4.1

Alternate pin functions

Each port pin can be assigned to one of multiple functions; it can, for instance, be an analog I/O, a digital peripheral function, an LCD pin, or a CAPSENSE™ pin. The pin assignments are shown in the following table.

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

Table 2

Port/Pin

P0.0

P0.1

P0.2

P0.3

P0.4

P0.5

P0.6

P0.7

P1.0

Pin assignments

Analog lpcomp.in_p[0] lpcomp.in_n[0] lpcomp.in_p[1] lpcomp.in_n[1] wco.wco_in

wco.wco_out

Smart I/O Alternate Function 1 Alternate Function 2 Alternate Function 3 Deep Sleep 1 tcpwm.tr_in[0] tcpwm.tr_in[1] srss.ext_clk

tcpwm.line[2]:1 tcpwm.line_compl[2]:1 tcpwm.line[3]:1 tcpwm.line_compl[3]:1 scb[1].uart_rx:0 scb[1].uart_tx:0 scb[1].uart_cts:0 scb[1].uart_rts:0 scb[0].uart_rx:1 scb[0].uart_tx:1 scb[0].uart_cts:1 scb[0].uart_rts:1 tcpwm.tr_in[2] tcpwm.tr_in[3] scb[1].i2c_scl:0 scb[1].i2c_sda:0 scb[0].i2c_scl:0 scb[0].i2c_sda:0

Deep Sleep 2 scb[0].spi_select1:0 scb[0].spi_select2:0 scb[0].spi_select3:0 scb[1].spi_mosi:1 scb[1].spi_miso:1 scb[1].spi_clk:1 scb[1].spi_select0:1 scb[0].spi_mosi:1 scb[0].spi_miso:1 scb[0].spi_clk:1 scb[0].spi_select0:1 scb[0].spi_select1:1 scb[0].spi_select2:1 scb[0].spi_select3:1

P1.7

P2.0

P2.1

P2.2

P2.3

prgio[0].io[0] prgio[0].io[1] prgio[0].io[2] prgio[0].io[3] tcpwm.line[4]:0 tcpwm.line_compl[4]:0 csd.comp

tcpwm.tr_in[4] tcpwm.tr_in[5] scb[1].i2c_scl:1 scb[1].i2c_sda:1 scb[1].spi_mosi:2 scb[1].spi_miso:2 scb[1].spi_clk:2 scb[1].spi_select0:2

Table 2

Port/Pin

P2.4

P2.5

P2.6

P2.7

P3.0

P3.1

Pin assignments

(continued)

Analog Smart I/O prgio[0].io[4] prgio[0].io[5] prgio[0].io[6] prgio[0].io[7] prgio[1].io[0]

Alternate Function 1 Alternate Function 2 Alternate Function 3 Deep Sleep 1 tcpwm.line[0]:1 tcpwm.line_compl[0]:1 tcpwm.line[1]:1 tcpwm.line_compl[1]:1 tcpwm.line[0]:0 scb[1].uart_rx:1 lpcomp.comp[0]:1 scb[1].i2c_scl:2 prgio[1].io[1] tcpwm.line_compl[0]:0 scb[1].uart_tx:1 scb[1].i2c_sda:2

P3.2

P3.3

P3.4

P3.5

P3.6

P3.7

P4.0

csd.vref_ext

P4.1

csd.cshieldpads

P4.2

csd.cmodpad

prgio[1].io[2] tcpwm.line[1]:0 prgio[1].io[3] tcpwm.line_compl[1]:0 prgio[1].io[4] tcpwm.line[2]:0 prgio[1].io[5] tcpwm.line_compl[2]:0 prgio[1].io[6] tcpwm.line[3]:0 prgio[1].io[7] tcpwm.line_compl[3]:0 scb[1].uart_cts:1 scb[1].uart_rts:1 scb[0].uart_rx:0 scb[0].uart_tx:0 scb[0].uart_cts:0 tcpwm.tr_in[6] tcpwm.tr_in[7] tcpwm.tr_in[8] tcpwm.tr_in[9] tcpwm.tr_in[10] tcpwm.tr_in[11] cpuss.swd_data

cpuss.swd_clk

lpcomp.comp[1]:1 scb[0].i2c_scl:1 scb[0].i2c_sda:1 lpcomp.comp[0]:0

P4.3

csd.csh_tank

scb[0].uart_rts:0 lpcomp.comp[1]:0

Deep Sleep 2 scb[1].spi_select1:1 scb[1].spi_select2:1 scb[1].spi_select3:1 scb[1].spi_mosi:0 scb[1].spi_miso:0 scb[1].spi_clk:0 scb[1].spi_select0:0 scb[1].spi_select1:0 scb[1].spi_select2:0 scb[1].spi_select3:0 scb[0].spi_mosi:0 scb[0].spi_miso:0 scb[0].spi_clk:0 scb[0].spi_select0:0