advertisement
32-Bit Arm ®
HT32F5828
Cortex ® -M0+ MCU
Bits
[25], [20],
[15], [10],
[5], [0]
Field
GEISTAn
Descriptions
Channel n Global Transfer Interrupt Status (n = 0 ~ 5)
0: No TE, TC, HT or BE event occurs
1: TE, TC, HT, or BE event occurs
This bit is set by hardware and is cleared by writing a “1” into the corresponding interrupt status clear bit, GEICLRn, in the PDMAISCR register. A Global Transfer
Event will occur if any of the BE, HT, TC and TE events occurs. Also clearing any of the BE, HT, TC and TE event interrupt flags will clear the GE interrupt flag. Note that if a “1” is written into the GEICLRn bit in the PDMAISCR register to clear the GE interrupt flag, the BE, HT, TC and TE event interrupt flags will also be cleared to 0 together with the GE interrupt status flag.
PDMA Interrupt Status Clear Register – PDMAISCR
This register is used to clear the corresponding interrupt status bits in the PDMAISR Register.
Offset: 0x128
Reset value: 0x0000_0000
Type/Reset
31 30 29 28 27 26 25 24
Reserved TEICLR5 TCICLR5 HTICLR5 BEICLR5 GEICLR5 TEICLR4
WC 0 WC 0 WC 0 WC 0 WC 0 WC 0
23 22 21 20 19 18 17 16
TCICLR4 HTICLR4 BEICLR4 GEICLR4 TEICLR3 TCICLR3 HTICLR3 BEICLR3
Type/Reset WC 0 WC 0 WC 0 WC 0 WC 0 WC 0 WC 0 WC 0
15 14 13 12 11 10 9 8
GEICLR3 TEICLR2 TCICLR2 HTICLR2 BEICLR2 GEICLR2 TEICLR1 TCICLR1
Type/Reset WC 0 WC 0 WC 0 WC 0 WC 0 WC 0 WC 0 WC 0
7 6 5 4 3 2 1 0
HTICLR1 BEICLR1 GEICLR1 TEICLR0 TCICLR0 HTICLR0 BEICLR0 GEICLR0
Type/Reset WC 0 WC 0 WC 0 WC 0 WC 0 WC 0 WC 0 WC 0
Bits
[29], [24],
[19], [14],
[9], [4]
[28], [23],
[18], [13],
[8], [3]
[27], [22],
[17], [12],
[7], [2]
Field
TEICLRn
TCICLRn
Descriptions
Channel n Transfer Error Interrupt Status Clear (n = 0 ~ 5)
0: No Operation
1: Clear the corresponding TEISTAn bit in the PDMAISR register
Writing a “1” into the TEICLRn bit will clear the TEISTAn status bit in the PDMAISR register. This bit will be automatically cleared to 0 after a “1” is written.
Channel n Transfer Complete Interrupt Status Clear (n = 0 ~ 5)
0: No Operation
1: Clear the corresponding TCISTAn bit in the PDMAISR register
Writing a “1” into the TCICLRn bit will clear the TCISTAn status bit in the PDMAISR register. This bit will be automatically cleared to 0 after a “1” is written.
HTRICLRn Channel n Half Transfer Interrupt Status Clear (n = 0 ~ 5)
0: No Operation
1: Clear the corresponding HTISTAn bit in the PDMAISR register
Writing a “1” into the HTRICLRn bit will clear the HTISTAn status bit in the PDMAISR register. This bit will be automatically cleared to 0 after a “1” is written.
Rev. 1.00 591 of 637 December 28, 2020
advertisement
Related manuals
advertisement