December. Holtek HT32F5828

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

I

2

S Interrupt Enable Register – I2SIER

This register contains the corresponding I 2 S interrupt enable bits.

Offset: 0x004

Reset value: 0x0000_0000

31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

Type/Reset

Type/Reset

15 14 13 12 11

Reserved

10 9 8

7 6 5 4 3 2 1 0

Reserved RXOVIEN RXUDIEN RXFTLIEN Reserved TXOVIEN TXUDIEN TXFTLIEN

RW 0 RW 0 RW 0 RW 0 RW 0 RW 0

Bits

[6]

[5]

[4]

[2]

[1]

[0]

Field

RXOVIEN

RXUDIEN

RXFTLIEN

TXOVIEN

TXUDIEN

TXFTLIEN

Descriptions

RX FIFO Overflow Interrupt Enable

0: Disable

1: Enable

RX FIFO Underflow Interrupt Enable

0: Disable

1: Enable

RX FIFO Trigger Level Interrupt Enable

0: Disable

1: Enable

TX FIFO Overflow Interrupt Enable

0: Disable

1: Enable

TX FIFO Underflow Interrupt Enable

0: Disable

1: Enable

TX FIFO Trigger Level Interrupt Enable

0: Disable

1: Enable

Rev. 1.00 354 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

I

2

S Clock Divider Register – I2SCDR

This register specifics the I 2 S clock divider ratio.

Offset: 0x008

Reset value: 0x0000_0000

31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

N_DIV

18 17 16

Type/Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0

15 14 13 12 11

X_DIV

10 9 8

Type/Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0

7 6 5 4 3 2 1 0

Y_DIV

Type/Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0

Bits

[23:16]

[15:8]

[7:0]

Field

N_DIV

X_DIV

Y_DIV

Descriptions

N divider for BCLK

0x00: divide 1

0x01: divide 2

...

0xFF: divide 256

Note: This bit should be configured when the I 2 S is disabled.

X divider for MCLK

(X = 1 ~ 255) && (X / Y ≤ 1)

Note: This bit should be configured when the I 2 S is disabled.

Y divider for MCLK

(Y = 1 ~ 255) && (X / Y ≤ 1)

Note: This bit should be configured when the I 2 S is disabled.

Rev. 1.00 355 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

I

2

S TX Data Register – I2STXDR

This register is used to specify the I 2 S transmitted data.

Offset: 0x00C

Reset value: 0x0000_0000

31 30 29 28 27

TXDR

26 25 24

Type/Reset WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0

23 22 21 20 19

TXDR

18 17 16

Type/Reset WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0

15 14 13 12 11

TXDR

10 9 8

Type/Reset WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0

7 6 5 4 3 2 1 0

TXDR

Type/Reset WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0

Bits

[31:0]

Field

TXDR

Descriptions

TX Data Register

I

2

S RX Data Register – I2SRXDR

This register is used to store the I 2 S received data.

Offset: 0x010

Reset value: 0x0000_0000

31 30 29 28 27

RXDR

26 25 24

Type/Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0

23 22 21 20 19 18 17 16

RXDR

Type/Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0

15 14 13 12 11

RXDR

10 9 8

Type/Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0

7 6 5 4 3 2 1 0

RXDR

Type/Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0

Bits

[31:0]

Field

RXDR

Descriptions

RX Data Register

Rev. 1.00 356 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Bits

[9]

[8]

[7:4]

I

2

S FIFO Control Register – I2SFCR

This register contains the related I 2 S FIFO control bits.

Offset: 0x014

Reset value: 0x0000_0000

31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12

Reserved

11 10 9 8

RXFRST TXFRST

Type/Reset

7 6 5

RXFTLS

4 3 2

RW 0 RW 0

1

TXFTLS

0

Type/Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0

[3:0]

Field

RXFRST

TXFRST

RXFTLS

TXFTLS

Descriptions

RX FIFO Reset

Set this bit to reset the RX FIFO.

TX FIFO Reset

Set this bit to reset the TX FIFO.

RX FIFO Trigger Level Select

0000: Trigger level is 0

0001: Trigger level is 1

...

0111: Trigger level is 7

1xxx: Trigger level is 8

When the data contained in the RX FIFO is equal to or greater than the level defined by the RXFTLS field, the RXFTL flag will be set.

TX FIFO Trigger Level Select

0000: Trigger level is 0

0001: Trigger level is 1

...

0111: Trigger level is 7

1xxx: Trigger level is 8

When the data contained in the TX FIFO is equal to or less than the level defined by the TXFTLS field, the TXFTL flag will be set.

Rev. 1.00 357 of 637 December 28, 2020