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32-Bit Arm ®
HT32F5828
Cortex ® -M0+ MCU
Type
Event
Condition
Master receives NACK
Description
No matter in address or data frame, once received an NACK signal will hold SCL line in master mode.
Eliminating Condition
Set TAR
Set STOP
Master sends NACK used in receiver mode
Occurred when receiving the last data byte in
Master receiver mode
(Note: Reference Figure 41, and RXNACK flag won’t be asserted in this case)
Set TAR
Set STOP
I
2
C Timeout Function
In order to reduce the occurrence of I 2 C lockup problem due to the reception of erroneous clock source, a timeout function is provided. If the I 2 C bus clock source is not received for a certain timeout period, then a corresponding I 2 C timeout flag will be asserted. This timeout period is determined by a 16-bit down-counting counter with a programmable preload value. The timeout counter is driven by the I 2 C timeout clock, f
I2CTO
, which is specified by the timeout prescaler field in the I2CTOUT register. The TOUT field in the I2CTOUT register is used to define the timeout counter preload value. The timeout function is enabled by setting the ENTOUT bit in the I2CCR register. The timeout counter will start to count down from the preloaded value if the ENTOUT bit is set to 1 and one of the following conditions occurs:
▆
▆
▆
The I 2 C master module sends a START signal.
The I 2 C slave module detects a START signal.
The RXBF, TXDE, RXDNE, RXNACK, GCS or ADRS flag is asserted.
The timeout counter will stop counting when the ENTOUT bit is cleared. However, the counter will also stop counting when one of the conditions listed as follows occurs:
▆
▆
▆
▆
The I 2 C slave module is not addressed.
The I 2 C slave module detects a STOP signal.
The I 2 C master module sends a STOP signal.
The ARBLOS or BUSERR flag in the I2CSR register is asserted.
If the timeout counter underflows, the corresponding timeout flag, TOUTF, in the I2CSR register will be set to 1 and a timeout interrupt will be generated if the relevant interrupt is enabled.
PDMA Interface
The PDMA interface is integrated in the I 2 C module. The PDMA function can be enabled by setting the TXDMAE or RXDMAE bit to 1 in the transmitter or receiver mode respectively. When the data register is empty in the transmitter mode and the TXDMAE bit is set to 1, the PMDA function will be activated to move data from a certain memory location into the I 2 C data register.
Similarly, when the data register is not empty in the receiver mode and the RXDMAE bit is set to
1, the PDMA function will also be activated to move data from the I 2 C data register to a specific memory location.
The DMA NACK control bit, DMANACK, is used to determine whether the NACK signal is sent or not when the I 2 C module operates in the master receiver mode and the PDMA function is enabled. If the DMANACK bit is set to 1 and the data has all been received and moved using the
PDMA interface, an NACK signal will automatically be sent out to properly terminate the data transfer.
For a more detailed description about the PDMA configurations, refer to the PDMA chapter.
Rev. 1.00 243 of 637 December 28, 2020
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