UART Test Register – URTSTR. Holtek HT32F5828

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

UART Test Register – URTSTR

This register controls the UART debug mode.

Offset: 0x028

Reset value: 0x0000_0000

31 30 29

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

21

13

5

28

20

27

Reserved

19

Reserved

12

4

Reserved

11

Reserved

3

Type/Reset

Bits

[1:0]

Field

LBM

Descriptions

Loopback Test Mode Select

00: Normal Operation

01: Reserved

10: Automatic Echo Mode

11: Loopback Mode

26

18

10

25

17

9

24

16

8

2 1 0

LBM

RW 0 RW 0

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Cortex ® -M0+ MCU

17

Smart Card Interface (SCI)

Introduction

The Smart Card Interface, SCI, is compatible with the ISO 7816-3 standard. This interface includes functions for card Insertion/Removal detection, SCI data transfer control logic and data buffers, internal Timer Counters and corresponding control logic circuits to perform the required Smart

Card operations. The Smart Card interface acts as a Smart Card Reader to facilitate communication with the external Smart Card. The overall functions of the Smart Card interface are controlled by a series of registers including control and status registers together with several corresponding interrupts which are generated to get the attention of the microcontroller for SCI transfer status.

As the complexity of ISO7816-3 standard data protocol does not permit comprehensive specifications to be provided in this datasheet, the reader should therefore consult other external information for a detailed understanding of this standard.

f

PCLK

6-bit Prescaler f

PSC_CK f

PSC_CK

11-bit Elementary

Time Unit

(ETU) f

ETU f

ETU

24-bit

Waiting Time

Counter

(WT) f

WT

9-bit

Guard Time

Counter

(GT) f

GT

SCI transfer

Control

Circuitry

Control

Circuitry

SCI TX/RX buffers

Clock

Control

I/O

Control

SCI_CLK

SCI_DIO

Interrupt Control

SCI Interrupt to NVIC

Figure 74. SCI Block Diagram

Card

Detection

SCI_DET

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Cortex ® -M0+ MCU

Features

▆

▆

▆

▆

▆

▆

▆

▆

▆

Supports ISO 7816-3 standard

Character Transfer Mode

1 transmit buffer and 1 receive buffer

11-bit ETU (elementary time unit) counter

9-bit guard time counter

24-bit general purpose waiting time counter

Parity generation and checking

Automatic character repetition on parity error detection in transmission and reception modes

Supports PDMA access at a transmission or reception completion

Functional Descriptions

To communicate with an external Smart Card, the integrated Smart Card Interface has a series of external pins known as SCI_CLK, SCI_DIO and SCI_DET. The SCI_CLK pin is the clock output signal used to communicate with the external Smart Card together with the serial data pin named SCI_DIO. The operation of the SCI_CLK and SCI_DIO pins can be selected to be the SCI data Transfer Mode which is driven automatically by the SCI control circuits or to be the Manual mode which is controlled by configuring the internal CLK and DIO register bits respectively by the application program. The SCI_DET pin is the external card detection input pin. Insertion or removal of the external Smart Card can be automatically detected and generate an interrupt signal which is sent to the microcontroller if the corresponding interrupt function is enabled.

For proper data transfer, some timing related procedures must be executed before the Smart

Card Interface can begin to communicate with the external card. There are three counters named

Elementary Time Unit Counter, ETU, Guard Time Counter, GT, and Waiting Time Counter, WT, which are used for the timing related functions in Smart Card Interface data transfer operations.

Elementary Time Unit Counter

The Elementary Time Unit, ETU, is an 11-bit up-counting counter which generates a clock denoted as f

ETU

to be used as the operating frequency source for the SCI data transmission and reception. The clock source of the ETU comes from the Smart Card clock , named f

PSC_CK

, which is derived from the 6-bit prescaler. The data transfer of the SCI is a character frame based protocol, f which basically consists of a Start bit, 8-bits of data and a Parity bit. The time period , t

ETU

(1/

ETU

), generated by the ETU, is the time unit for a character bit. There is a register related to the

Elementary Time Unit known as the ETUR register which stores the expected contents of the

ETU. Each time the ETUR register is written, the ETU circuitry will reload the new written value and restart counting. The elementary time unit t

ETU

is obtained from the following formula which defines the bit rate in the ISO 7816-3 standard specification.

1etu = t

ETU

=

F i

D i

× f

1

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Cortex ® -M0+ MCU where:

▆

▆

▆

▆ etu is the nominal duration of the data bit on the signal SCI_DIO provided to the card by the interface

Di is the bit-rate adjustment factor

Fi is the clock rate conversion factor f is the frequency value of the clock signal SCI_CLK provided to the card by the interface

D i is an encoded decimal value based on a 4-bit field, named DI, as represented in the accompanying table.

Table 48. DI Field Based Di Encoded Decimal Values

DI field 0001 0010 0011 0100 0101 0110 0111 1000 1001

Di (decimal) 1 2 4 8 16 32 64 12 20

F i is an encoded decimal value based on a 4-bit field, named FI, as represented in the following table.

Table 49. FI Field Based F i

Encoded Decimal Values

FI field 0000 0001 0010 0011 0100 0101 0110 1001 1010 1011 1100 1101

Fi (decimal) 372 372 558 744 1116 1488 1860 512 768 1024 1536 2048

The values of FI and DI, as they appear in the preceding tables, will be obtained from the Answerto-Reset packet sent from the external Smart Card to the Smart Card Interface the first time the external Smart Card is inserted. When the SCI receives the FI and DI information, the Fi and

Di value s can be obtained by looking up the preceding two tables. After the Fi and Di values are obtained, the value which should be written into the ETUR register can be calculated by Fi/Di. The following table shows the possible ETU values obtained by the F i

/D i

ratio.

64

12

20

16

32

4

8

Table 50. Possible ETU Values Obtained with the Fi/Di Ratio

Fi

Di

1

2

372 558 744 1116 1488 1860 512 768 1024 1536 2048

372

186

558

279

744 1116 1488 1860 512

372 558 744 930 256

93 139.5

186

46.5

69.75

93

279 372 465

139.5

186 232.5

23.25 34.87

46.5

69.75

93 116.2

11.62 17.43 23.25 34.87

46.5

58.13

128

64

32

16

5.81

8.72

11.63 17.44 23.25 29.06

31 46.5

62 93 124 155

8

42.66

18.6

27.9

37.2

55.8

74.4

93

12

64

25.6

38.4

768 1024 1536 2048

384 512 768 1024

192

96

48

24

256

128

64

32

384

192

96

48

512

256

128

64

16

85.33

51.2

24

128

76.8

32

170.6

102.4

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Compensation mode

As the value of the ETUR register is obtained by the above procedure, the calculation results of the value may not be an integer. If the calculation result is not an integer and is less than the integer n but greater than the integer (n-1), either the integer n or (n-1) should be written into the ETUR register depending upon whether the result is closer to integer n or (n-1). The integer n mentioned here is a decimal.

If the calculation result is close to the value of (n-0.5), the compensation mode should be enabled by setting the compensation enable control bit, COMP, in the ETUR register to 1 for successful data transfer. When the result is close to the value of (n-0.5) and the compensation mode is enabled, the value written into the ETUR register should be n. The ETU circuitry will then generate the time unit sequence with n clock cycles and next (n-1) clock cycles alternately and so on. This results in an average time unit of (n-0.5) clock cycles and allows a time granularity down to a half clock cycle. Note that the ETU will reload the ETUR register value and restart counting at the time when the Start bit appears in the SCI data Transfer Mode.

SCI_DIO

Start bit Parity bit

Data bits

P n n t

ETU n n

Character n n n n n n

SCI_CLK COMP=0

SCI_CLK n n-1 n n-1 n n-1 n n-1 n n-1

SCI_CLK n-1 n n-1 n n-1 n n-1 n n-1

Note: The ETUR register value = n, i.e. 1 t

ETU

= n clocks in this example.

n

Figure 75. Character Frame and Compensation Mode

COMP=1

(Average time unit= n-0.5)

Guard Time Counter

The Guard Time Counter, GT, is a 9-bit up-counting counter which generates a minimum time duration known as a character frame, denoted as t

GT

, between the leading edges of two consecutive characters in the SCI data transfer. The clock source of the guard time counter comes from the

ETU , named f

ETU

in the block diagram. There is a register related to the guard time counter known as the GTR register, which stores the expected value of the guard time counter. The guard time value will be reloaded at the end of the current guard time period. Note that the guard time between the last character received from the Smart Card and the next character transmitted by the SCI circuitry which should be properly managed by the application program. There is no guard time insertion when the first character is transmitted.

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Start

Char 0

SCI_DIO t

GT

Smart Card → SCI

Figure 76. Guard Time Duration

Start

Char 1 t

GT

Start Start

Char n t

GT t

GT

Start

Char 0 t

GT

SCI → Smart Card

Start

Char 1 t

GT

Start

SCI_DIO

Waiting Time Counter

The Waiting Time counter, WT, is a 24-bit down counting counter which generates a maximum time duration, denoted as t from the ETU

WT

, for data transfer. The clock source of the waiting time counter comes

and is named f

ETU

.

There is a register for the waiting time counter known as the WTR register which stores the expected waiting time counter value. The waiting time counter can be used in both the SCI data

Transfer Mode and manual mode and can reload the value for specific conditions. The function of the waiting time counter is controlled by the WTEN bit in the CR register. When the SCI is configured to be operated in the SCI data Transfer Mode and the waiting time counter is enabled by setting the WTEN bit to 1, the updated WTR register value will be loaded into the waiting time counter when the Start bit is detected. Note that the WTEN bit should not be set to 1 to enable the waiting time counter in the SCI data Transfer Mode until after the external Smart Card is inserted.

If the SCI is configured to operate in the manual mode, the waiting time counter can be used as a general purpose timer and this timer is enabled or disabled by setting or clearing the WTEN bit.

The updated WTR register value will not be loaded into the waiting time counter if the waiting time counter is enabled. When the waiting time counter is disabled by setting the WTEN bit to 0 and an updated value is written into the WTR register, the new value will immediately be loaded into the waiting time counter and then the counter will start to count after the WTEN bit is again set to 1.

Software can change the Waiting Time value on-the-fly. For example, in T = 1 mode, the value of the Block Waiting Time, t

BWT

, should be written into the WTR register before the Start bit of the last transmitted character occurs. After the transmission of the last character is completed, software should write the Character Waiting Time value, t

CWT

, into the WTR register.

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SCI_DIO Char 0

SCI → Smart

Card

Program the BWT

Start bit

Char 1

Program the CWT

Char n t

BWT

BWT is reloaded on Start bit

Start bit

Char 0 t

CWT

Smart Card → SCI

Figure 77. Character and Block Waiting Time Duration – CWT and BWT

Char 1 SCI_DIO

Card Clock and Data Selection

The SCI communicates with an external Smart Card using a series of external pins. These are the serial data pin, SCI_DIO, output clock pin, SCI_CLK, and the Card Detection input pin, SCI_DET.

The SCI serial data pin, named SCI_DIO, can be controlled by the SCI hardware circuitry or the software control bits depending upon whether the SCI is operated in the SCI Transfer Mode or in the Manual Mode. The mode selection is determined by the SCIM bit in the CR register. The SCI_

DIO pin status is controlled by the CDIO bit in the CCR register when the SCI is configured to operate in the Manual mode by clearing the SCIM bit in the CR register. In the Manual Mode the

SCI_DIO pin status is a copy of the CDIO bit. However, when the SCI is configured to operate in the SCI Transfer Mode, the SCI_DIO pin status is determined by the SCI transfer circuitry.

The SCI clock output pin named SCI_CLK can be controlled by the 6-bit SCI prescaler or the software control bits depending upon the condition of the CLKSEL bit in the CCR register. The

SCI_CLK pin status is controlled by the CCLK bit in the CCR register when the CLKSEL bit is cleared to 0. The SCI_CLK pin status is a copy of the CCLK bit. However, when the CLKSEL bit is set to 1, the SCI_CLK signal is sourced from the 6-bit prescaler output. The prescaler division ratio is determined by the PSC field in the PSCR register.

Card Detection

When an external Smart Card is inserted, the internal card detector can detect this insertion operation and generate a card insertion interrupt if the corresponding interrupt enable control bit, CARDIRE, in the IER register is set to 1. Similarly, if the card is removed, the internal card detector can also detect the removal and consequently generate a card removal interrupt when the corresponding interrupt function is enabled by setting the control bit, CARDIRE, in the IER register, to 1.

The card detector can support two kinds of card detect switch mechanisms. One is a normally open switch mechanism when the card is not present and the other is a normally closed switch mechanism. After noting which card detect switch mechanism type is used, the card switch selection should be configured by setting the selection bit, DETCNF, in the CR register to correctly detect the card presence. No matter what type of the card switch is selected, by configuring the

DETCNF bit, the card Insertion/Removal flag, CPREF, in the SR register will be set to 1 when the card is actually present on the SCI_DET pin. Note that there are no hardware de-bounce circuits in the card detector. Any change of the SCI_DET pin level will cause the CPREF bit to change. The required de-bounce time should be handled by the application program.

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CPREF

Edge

Detection

Card Insertion / Removal

Interrupt request

0

1

SCI_DET

CARDIRE

Figure 78. SCI Card Detection Diagram

DETCNF

SCI Data Transfer Mode

The SCI data transfer with the external Smart Card is implemented with two operating modes. One is the SCI mode while the other is the Manual Mode. The data Transfer Mode is selected by the

SCI mode selection bit, SCIM, in the CR register. When the SCIM bit is set to 1, the SCI mode is enabled and data will automatically be transferred by the SCI transfer circuitry. Otherwise, data transfer operates in the Manual Mode if the SCIM bit is cleared to 0. The SCI transfer interface is a half-duplex interface and communicates with the external Smart Card via the SCI_CLK and SCI_

DIO pins. After a reset condition the SCI transfer interface is in the reception mode but the SCI transfer operation is disabled. When the SCI mode is enabled, data transfer is driven by the SCI transfer circuitry automatically through the SCI_CLK and SCI_DIO pins.

There are two data registers related to data transmission and reception, TXB and RXB, which store the data to be transmitted and received respectively. If a character is written into the TXB register in the SCI Transfer Mode, the SCI transfer interface will automatically switch to the Transmission

Mode from the reception mode after a reset. When the SCI transmission or reception has finished, the corresponding request flag, named TXCF or RXCF, in the SR register is set to 1. If the transmit buffer is empty, the transmit buffer empty flag, TXBEF, in the SR register will be set to 1.

Parity Check Function

The SCI transfer interface supports a parity generator and a parity check function. As the parity error occurs during a data transfer, the corresponding request flag, named PARF in the SR register, will be set to 1. Once the PARF bit is set to 1, the parity error pending flag, PARP, in the

IPR register will also be set to 1 if the relevant interrupt control bit, PARE, in the IER register is enabled.

If the data transmitted by the SCI is received by the external Smart Card without a parity error, the

SCI transmission request flag, TXCF, will be set to 1 and the SCI parity error request flag, PARF, will be cleared to 0. If the data transmitted by the external Smart Card is received by the SCI without a parity error, the SCI reception request flag, RXCF, will be set to 1 and the parity error flag, PARF, will remain zero.

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Repetition Function

There is a Character Repetition function supported by the SCI transfer circuitry when a parity error occurs. The Character Repetition function is enabled by setting the CREP bit in the CR register to 1. A repetition function will then be activated when a parity error occurs during a data transfer.

The repetition time number can be selected to be 4 or 5 by configuring the RETRY bit in the CR register.

When the CREP bit is set to 1, the character repetition function will be activated. Taking a 4 time repetition as an example, when the CREP bit is set to 1 and the RETRY bit is set to 1, in the

Transmission Mode, the SCI will repeatedly transmit the data a maximum of 4 times when an error signal occurs. However, if the SCI is informed that there is still an error signal during the 4 transmissions, the parity error flag PARF will be set to 1 after the same data has been transmitted

4 times but the TXCF flag will not be set. At this time the data in the transmit buffer will be loaded into the transmit shift register and the transmit buffer will be empty which will result in the

TXBEF flag being set to 1.

Similarly, when the SCI operates in the reception mode, it will inform the external Smart Card that there is a parity error for a maximum of 4 times if the character repetition function is enabled. If the SCI informs the external Smart Card that there is still an error signal for the 4 receptions, the parity error flag, PARF, will be set to 1 together with the reception request flag, RXCF.

If the CREP bit is cleared to 0, the character repetition function will be disabled. When the SCI operates in the reception mode, both the PARF and RXCF bits will be set to 1 as data with a parity error has been received. If the SCI is informed that there is a parity error in the Transmission

Mode, the PARF bit will be set to 1 but the TXCF bit will not be set.

Manual Data Transfer Mode

When the SCIM bit is cleared to 0, data will be transferred in the Manual Mode. In the Manual

Mode, the data is controlled by the control bit, CDIO, in the CCR register. The CDIO bit value will be reflected immediately on the SCI_DIO pin in the Manual Mode. Note that in the Manual

Mode the character repetition function can not be used as well as the related flags and all the data transfer is handled by the application program. The clock used to drive the external Smart Card that appears on the SCI_CLK pin can be derived from the internal clock source , which is the 6-bit prescaler output, f

PSC_CK

, or from the control bit, CCLK, in the CCR register . The clock source is selected using the bit, CLKSEL, in the CCR register. When CLKSEL bit is set to 1, the clock used to drive the Smart Card will be sourced from the 6-bit prescaler output, f managed manually, the CLKSEL bit should first be cleared to 0 and then the value of the CCLK bit will be present in the SCI_CLK pin.

PSC_CK

. If the clock is to be

Data Transfer Direction Convention

If the direction convention used by the Smart Card is the same as the convention used by the SCI, the SCI will generate a reception interrupt if the reception interrupt is enabled without a parity error flag. Otherwise, the SCI will generate a reception interrupt and the parity error flag will be asserted. By checking the parity error flag, the SCI can know if the data direction convention is correct or not.

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Interrupt Generator

There are several conditions for the SCI to generate an SCI interrupt. When these conditions are met, an interrupt signal will be generated to obtain the attention of the microcontroller. These conditions are a Smart Card Insertion/Removal, a Waiting Time Counter Underflow, a Parity error, an end of a Character Transmission or Reception and an empty Transmit buffer. When a

Smart Card interrupt is generated by any of these conditions, then if the SCI global interrupt and the corresponding SCI interrupt are together enabled, the program will jump to the corresponding interrupt vector where it can be serviced before returning to the main program.

For SCI interrupt events, there are corresponding pending flags which can be masked by the relevant interrupt enable control bit. When the related interrupt enable control is disabled, the corresponding interrupt pending flag will not be affected by the request flag and no interrupt will be generated. If the related interrupt enable control is enabled, the relevant interrupt pending flag will be affected by the request flag and then the interrupt will be generated. The pending flag register, named IPR, is read only and once the pending flag is read by the application program, it will be automatically cleared while the related request flag should be cleared by the application program manually.

For an SCI Interrupt to be serviced, in addition to the bits for the corresponding interrupt enable control in the SCI being set, the SCI global interrupt enable control bit in the NVIC must also be set. If this SCI global interrupt control bit is not set, then no SCI interrupt will be serviced.

Card Insertion/Removal

Request flag CPREF

Transmit Buffer Empty request flag TXBEF

End of Transmission

Request flag TXCF

End of Reception

Request flag RXCF

Parity Error

Request flag PARF

WTC Underflow

Request flag WTF

CSR Register

Figure 79. SCI Interrupt Structure

CARDIRE

0

1

0

1

TXBEE

0

1

TXCE

0

1

RXCE

0

1

PARE

0

1

WTE

CIER Register

Card Insertion/Removal pending flag CARDIRP

Transmit Buffer Empty pending flag TXBEP

End of Transmission pending flag TXCP

End of Reception pending flag RXCP

Parity Error pending flag PARP

WTC Underflow pending flag WTP

CIPR Register

SCI Interrupt Signal sent to NVIC

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PDMA Interface

The PDMA interface is integrated in the SCI module. The PDMA function can be enabled by setting the TXDMA or RXDMA bit to 1 in the transmitter or receiver mode respectively. When the transmit buffer is empty which results in the transmit buffer empty flag, TXBEF, being asserted and the TXDMA bit is set to 1, the PDMA function will be activated to move data from a certain memory location into the SCI Transmit buffer. Similarly, when the SCI receives a character which results in the character received flag, RXCF, being asserted and the RXDMA bit is set to 1, the

PDMA function will be activated to move data from the SCI Receive buffer to a specific memory location.

For a more detailed descriptions on the PDMA configurations, refer to the PDMA chapter.

Register Map

There are several registers associated with the Smart Card function. Some of these registers control the SCI overall function as well as the interrupts, while some of the registers contain the status bits which indicate the Smart Card data transfer situation and error conditions. Also there are two registers for the SCI transmission and reception respectively to store the data received from or to be transmitted to the external Smart Card. The following table shows the SCI register list and reset values.

Table 51. SCI Register Map

Register

CR

SR

CCR

ETUR

Offset

0x000

0x004

0x008

0x00C

Description

SCI Control Register

SCI Status Register

SCI Contact Control Register

SCI Elementary Time Unit Register

GTR

WTR

IER

IPR

TXB

RXB

PSCR

0x010

0x014

0x018

0x01C

0x020

0x024

0x028

SCI Guard Time Register

SCI Waiting Time Register

SCI Interrupt Enable Register

SCI Interrupt Pending Register

SCI Transmit Buffer

SCI Receive Buffer

SCI Prescaler Register

Reset Value

0x0000_0000

0x0000_0080

0x0000_0008

0x0000_0174

0x0000_000C

0x0000_2580

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

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Register Descriptions

SCI Control Register – CR

This register contains the SCI control bits.

Offset: 0x000


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

Type/Reset

Type/Reset

15 14 13 12

Reserved

11 10 9

RXDMA

8

TXDMA

7 6

Reserved DETCNF

5

ENSCI

4

RETRY

3

SCIM

2

WTEN

RW 0 RW 0

1

CREP

0

CONV

RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0

Bits

[9]

[8]

[6]

[5]

[4]

Field

RXDMA

TXDMA

DETCNF

ENSCI

RETRY

Descriptions

SCI reception DMA request enable

0: SCI reception DMA request is disabled

1: SCI reception DMA request is enabled

SCI transmission DMA request enable control

0: SCI transmission DMA request is disabled

1: SCI transmission DMA request is enabled

Card switch type selection

0: Switch is normally opened if no card is present

1: Switch is normally closed if no card is present

DETCNF

0

0

SCI_DET pin

1

0

STATUS

No card insert

Card insert

1

1

1

0

Card insert

No card insert

This bit is set and cleared by the application program to configure the card detector switch type.

SCI finite state machine enable bit

0: SCI FSM is disabled and forced to its initial state

1: SCI FSM is enabled

Character transfer repetition time selection for a parity error condition

0: Data transfer 5 times when parity error occurs

1: Data transfer 4 times when parity error occurs

The bit is available only when the CREP bit is set to 1. When this bit is set to 1, the data will be transmitted or received 4 times once a parity error occurs. If the bit is cleared to 0, the data will be transferred 5 times if a parity error occurs.

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Bits

[3]

[2]

[1]

[0]

Field

SCIM

WTEN

CREP

CONV

Descriptions

SCI Mode Selection

0: SCI data transfer in manual mode

1: SCI data transfer in SCI mode

This bit is set and cleared by the application program to select the SCI data Transfer

Mode. If it is cleared to 0, the SCI_DIO pin status is the same as the value of the

CDIO bit in the CCR register. If it is set to 1, the SCI_DIO pin is driven by the internal

SCI control circuitry. Before the data transfer type is switched from the Manual Mode to the SCI Mode, the CDIO bit must be set to 1 to avoid an SCI malfunction.

Waiting Time Counter enable control

0: Waiting Time Counter stops counting

1: Waiting Time Counter starts counting

The WTEN bit is set and cleared by the application program. When the WTEN bit is cleared to 0, a write access to the WTR register will load the value into the waiting time counter. If it is set to 1, the waiting time counter is enabled and automatically reloaded with the value at each start bit occurrence.

Automatic character repetition enable control for a parity error condition

0: No retry on parity error

1: Automatic retry on parity error

The CREP bit is set and cleared by the application program. When the CREP bit is cleared to 0, both the RXCF and PARF flags will be set when a parity error occurs in the reception mode after the data is received. However, in the Transmission Mode, the PARF flag will be set but the TXCF flag will not be set when a parity error occurs.

If the CREP bit is set to 1, a character transfer will automatically be activated 4 or 5 times depending upon the RETRY bit value. In the Transmission Mode the character will be re-transmitted if the transmitted data has a parity error. Here the parity error flag, PARF, will be set at the end of the 4 th or 5 th transmission without the TXCF bit being set. In the reception mode if the received data has a parity error, the SCI will inform the external Smart Card for 4 or 5 times and then the PARF and RXCF flags will both be set at the end of the 4 th or 5 th reception.

Data direction convention select

0: LSB is transferred first; a data “1” is a logic high level on the SCI_DIO pin and the parity bit is added after the MSB.

1: MSB is transferred first; a data “1” is a logic low level on the SCI_DIO pin and the parity bit is added after the LSB.

This bit is set and cleared by the application program to select if the data is transmitted LSB or MSB first. When the data direction convention is the same as the data direction specified by the external Smart Card, only the RXCF flag will be set to 1 without a parity error. Otherwise, both the RXCF and PARF flags will be set to 1 after the data is received.

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HT32F5828

Cortex ® -M0+ MCU

SCI Status Register – SR

This register contains the SCI status bits.

Offset: 0x004


31 30

Type/Reset

23 22

Type/Reset

15 14

Type/Reset

7

TXBEF

6

CPREF

Type/Reset RO 1 RO 0

29

21

13

5

28

20

27

Reserved

19

Reserved

26

18

25

17

24

16

12 11

Reserved

10 9 8

4 reserved

3

WTF

2

TXCF

1

RXCF

0

PARF

RO 0 W0C 0 RO 0 W0C 0

Bits

[7]

[6]

[3]

[2]

Field

TXBEF

CPREF

WTF

TXCF

Descriptions

Transmit Buffer Empty Request Flag

0: Transmit buffer is not empty

1: Transmit buffer is empty

This bit is used to indicate if the transmit buffer is empty and is set or cleared by hardware automatically.

Card Presence Request Flag

0: No card is present

1: A card is present

This bit is used to indicate if a card is present and is set or cleared by hardware automatically. The card presence detection function is enabled after the ENSCI bit is set.

Waiting Time Counter Underflow Request Flag

0: No Waiting Time Counter underflow

1: The Waiting Time Counter underflows

This bit is set and cleared by the application program and indicates if the Waiting

Time Counter underflows.

Character Transmission Request Flag.

0: No character transmitted

1: A character has been transmitted

This bit is set by hardware and cleared by writing a “0” into it.

Rev. 1.00 329 of 637 December 28, 2020

32-Bit Arm ®

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Cortex ® -M0+ MCU

Bits

[1]

[0]

Field

RXCF

PARF

Descriptions

Character Received Request Flag.

0: No character received

1: A character has been received

This bit is set by hardware and cleared after a read access to the RXB register by the application program. The RXCF bit will be set to 1 when a character is received regardless of the result of the parity check.

When the character has been received, the received data stored in the RXB register should be moved to the data memory as specified by the application program. If the contents of the RXB register are not read before the end of the next character to be shifted in, the data stored in the RXB register will be overwritten.

Parity Error Request Flag.

0: No parity error occurs

1: Parity error has occurred

This bit is set by hardware and cleared by writing a “0” into it. When a character is received, the parity check circuitry will check that the parity is correct or not. If the result of the parity check is not correct, the parity error request flag, PARF, will be set to 1. Otherwise, the PARF bit will remain zero. In the Transmission Mode when the SCI is informed that there is a parity error in the transmitted character by the external Smart Card, the PARF bit will also be set to 1.

SCI Contact Control Register – CCR

This register specifies the SCI pin setting and clock selection.

Offset: 0x008


30 29 28 31

Type/Reset

23

Type/Reset

15

Type/Reset

7

CLKSEL

Type/Reset RW 0

22

14

6

21

13

5

Reserved

20

12

4

27

Reserved

19

Reserved

26

18

11

Reserved

10

3

CDIO

2

CCLK

RW 1 RW 0

Bits

[7]

Field

CLKSEL

25

17

9

1

24

16

8

0

Reserved

Descriptions

Card Clock Selection

0: The CCLK bit content is present on the external SCI_CLK pin

1: The clock output on the external SCI_CLK pin is sourced from the f

PSC_CK by the application program. It is recommended that to activate the clock at a known level a certain value should be first programmed into the CCLK bit before the

CLKSEL bit is switched from 1 to 0.

clock

This bit is used to select the external SCI_CLK pin clock source. It is set and cleared

Rev. 1.00 330 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Bits

[3]

[2]

Field

CDIO

CCLK

Descriptions

SCI_DIO pin control

0: SCI_DIO pin is logic level 0

1: SCI_DIO pin in open-drain condition

This bit is available only when the SCIM bit in the CR register is cleared to 0 to configure the SCI to operate in the Manual Transfer Mode. It is set and cleared by application program to control the external SCI_DIO pin status in the Manual Mode.

Reading this bit will return the present status of the SCI_DIO pin.

SCI_CLK pin control.

0: SCI_CLK pin is logic level 0

1: SCI_CLK pin is logic level 1

This bit is available when the SCI operates in the Manual Transfer Mode. It is set and cleared by application program to control the external SCI_CLK pin status in the

Manual Mode. Reading this bit will return the current value in the register and not the present status of the external SCI_CLK pin. To ensure that the clock remains at a known level a certain value should be first programmed into the CCLK bit before the CLKSEL bit is switched from 1 to 0.

SCI Elementary Time Unit Register – ETUR

The register specifies the value determined by the formula described in the ETU section. It also includes the

Compensation function enable control bit for the ETU time granularity.

Offset: 0x00C


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15

COMP

Type/Reset RW 0

14 13 12

Reserved

11 10 9

ETU

8

RW 0 RW 0 RW 1

7 6 5 4 3

ETU

2 1 0

Type/Reset RW 0 RW 1 RW 1 RW 1 RW 0 RW 1 RW 0 RW 0

Bits

[15]

Field

COMP

Descriptions

Elementary Time Unit Compensation mode enable control

0: Compensation mode is disabled

1: Compensation mode is enabled

This bit is set and cleared by application program and used to control the ETU compensation function. For more details regarding the compensation function consult the Elementary Time Unit section.

Rev. 1.00 331 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Bits

[10:0]

Field

ETU

Descriptions

ETU value for a character data bit

This field is configured by the application program to modify the ETU time duration.

Note that the value of ETU must be in the range of 0x00C to 0x7FF. To obtain the maximum ETU decimal value of 2048, a 0x000 value should be written into this bit field.

SCI Guard Time Register – GTR

This register specifies the guard time value obtained from the Answer-to-Reset packet described in the Guard

Time Counter section.

Offset: 0x010

Reset value: 0x0000_000C

31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

Type/Reset

15

7

14

6

13

5

12

Reserved

4

11

3

GT

10

2

9

1

8

GT

RW 0

0


Bits

[8:0]

Field

GT

Descriptions

Character Guard Time value

This field is configured by the application program to modify the guard time duration.

The updated GT value will be loaded into the GT counter at the end of the current guard time period. Note that the GT value must be in the range from 0x00C to

0x1FF.

Rev. 1.00 332 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

SCI Waiting Time Register – WTR

This register specifies the waiting time value obtained from the Answer-to-Reset packet described in the Waiting

Time Counter section.

Offset: 0x014


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

WT

18 17 16


15 14 13 12 11

WT

10 9 8


7 6 5 4 3 2 1 0

WT


Bits

[23:0]

Field

WT

Descriptions

Character Waiting Time value expressed in ETU (0/16777215).

This field is configured by the application program to modify the waiting time duration. The reload conditions of the updated waiting time counter value are described in the waiting time counter section. Refer to the waiting time counter section for more details. Note that the WT value can range from 0x00_0000 to 0xFF_FFFF.

Rev. 1.00 333 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

SCI Interrupt Enable Register – IER

This register specifies the interrupt enable control bits for all of the interrupt events in the SCI.

Offset: 0x018


29 31 30

Type/Reset

23 22

Type/Reset

15 14

Type/Reset

7 6

TXBEE CARDIRE

Type/Reset RW 0 RW 0

21

13

5

28

20

27

Reserved

19

Reserved

26

18

25

17

24

16

12 11

Reserved

10 9 8

4

Reserved

3

WTE

2

TXCE

1

RXCE

0

PARE

RW 0 RW 0 RW 0 RW 0

Bits

[7]

[6]

[3]

[2]

Field

TXBEE

Descriptions

Transmit buffer empty interrupt enable control

0: Disabled

1: Enabled

This bit is set and cleared by application program and is used to control the Transmit

Buffer Empty interrupt. If this bit is set to 1, the transmit buffer empty interrupt will be generated when the transmit buffer is empty.

CARDIRE Card Insertion / Removal interrupt enable control

0: Disabled

1: Enabled

This bit is set and cleared by application program and is used to control the card insertion/removal interrupt. If this bit is set to 1, the card insertion/removal interrupt will be generated when the external Smart Card is inserted or removed.

WTE Waiting Timer Underflow interrupt enable control

0: Disabled

1: Enabled

This bit is set and cleared by the application program and is used to control the

Waiting Timer underflow interrupt. If this bit is set to 1, the waiting time counter underflow interrupt will be generated when the waiting time counter underflows.

TXCE Character Transmission Completion interrupt enable control

0: Disabled

1: Enabled


Character Transmission Completion interrupt. If this bit is set to1, the Character

Transmission Completion interrupt will be generated at the end of the character transmission.

Rev. 1.00 334 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Bits

[1]

[0]

Field

RXCE

PARE

Descriptions

Character Reception Completion interrupt enable control

0: Disabled

1: Enabled


Character Reception Completion interrupt. If this bit is set to 1, the Character

Reception Completion interrupt will be generated at the end of the character reception.

Parity Error interrupt enable control

0: Disabled

1: Enabled

This bit is set and cleared by the application program and is used to control the parity error interrupt. if this bit is set to 1, the Parity Error interrupt will be generated when a parity error occurs.

SCI Interrupt Pending Register – IPR

This register contains the interrupt pending flags for all of the interrupt events in the SCI. These pending flags can be masked by the corresponding interrupt enable control bits.

Offset: 0x01C


29 31 30

Type/Reset

23 22

Type/Reset

15 14

Type/Reset

7 6

TXBEP CARDIRP

Type/Reset RC 0 RC 0

21

13

5

28

20

27

Reserved

19

Reserved

26

18

25

17

24

16

12 11

Reserved

10 9 8

4

Reserved

3

WTP

2

TXCP

1

RXCP

0

PARP

RC 0 RC 0 RC 0 RC 0

Bits

[7]

Field

TXBEP

Descriptions

Transmit Buffer Empty interrupt pending flag

0: No interrupt pending

1: Interrupt pending

This bit is set by hardware and cleared by a read access to this register using the application program. This bit is used to indicate if there is a Transmit Buffer Empty interrupt pending or not. If the Transmit Buffer is empty and the corresponding interrupt enable control bit is set to 1, this bit will be set to 1 to indicate that the transmit buffer empty interrupt is pending.

Rev. 1.00 335 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Bits

[6]

[3]

[2]

[1]

[0]

Field Descriptions

CARDIRP Card Insertion/Removal interrupt pending flag



This bit is set by hardware and cleared by a read access to this register using the application program. It is used to indicate if there is an external Smart Card insertion/ removal interrupt pending or not. If an external Smart Card is inserted or removed and the corresponding interrupt enable control bit is set to 1, this bit will be set to 1 to indicate that the Card insertion/removal interrupt is pending.

WTP Waiting Timer Underflow interrupt pending flag



This bit is set by hardware and cleared by a read access to this register using the application program. It is used to indicate if there is a waiting time counter underflow interrupt pending or not. If the waiting time counter underflows and the corresponding interrupt enable control bit is set to 1, this bit will be set to 1 to indicate that the waiting time counter underflow interrupt is pending.

TXCP

RXCP

PARP

Character Transmission Completion interrupt pending flag



This bit is set by hardware and cleared by a read access to this register using the application program. It is used to indicate if there is a Character Transmission

Completion interrupt pending or not. If a character has been transmitted and the related interrupt enable control bit is set to 1, this bit will be set to 1 to indicate that the character transmission completion interrupt is pending.

Character Reception Completion interrupt pending flag



This bit is set by hardware and cleared by a read access to this register using the application program. It is used to indicate if there is a Character Reception

Completion interrupt pending or not. If a character has been received and the relevant interrupt enable control bit is set to 1, this bit will be set to 1 to indicate that the character reception completion interrupt is pending.

Parity Error interrupt pending flag



This bit is set by hardware and cleared by a read access to this register using the application program. It is used to indicate if there is a Parity Error interrupt pending or not. If the parity error occurs and its interrupt enable control bit is set to 1, this bit will be set to 1 to indicate that the parity error interrupt is pending.

Rev. 1.00 336 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

SCI Transmit Buffer – TXB

This register is used to store the SCI data to be transmitted.

Offset: 0x020


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

Reserved

10 9 8

Type/Reset

7 6 5 4 3

TB

2 1 0


Bits

[7:0]

Field

TB

Descriptions

SCI data byte to be transmitted

SCI Receive Buffer – RXB

This register is used to store the SCI received data.

Offset: 0x024


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

Reserved

10 9 8

Type/Reset

7 6 5 4 3

RB

2 1 0

Type/Reset RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0 RO 0

Bits

[7:0]

Field

RB

Descriptions

SCI Received data byte

Rev. 1.00 337 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

SCI Prescaler Register – PSCR

This register specifies the prescaler division ratio which is used the SCI internal clock.

Offset: 0x028


31

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

30

22

29

21

28

20

27

Reserved

19

Reserved

26

18

25

17

24

16

14 13 12 11

Reserved

10 9 8

6

Reserved

5 4 3 2

PSC

1 0

RW 0 RW 0 RW 0 RW 0 RW 0 RW 0

Bits

[5:0]

Field

PSC

Descriptions

SCI prescaler division ratio

0: f

PSC_CK

= f

PCLK

1~63: f

PSC_CK 2 ×

PCLK

PSC

Rev. 1.00 338 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

18

Inter-IC Sound (I

2

S)

Introduction

The I 2 S is a synchronous communication interface that can be used as a master or slave to exchange data with other audio peripherals, such as ADCs or DACs. The I 2 S supports a variety of data formats. In addition to the stereo I 2 S-justified, Left-justified and Right-justified modes, there are mono PCM modes with 8/16/24/32-bit sample size. When the I 2 S operates in the master mode, then when using the fractional divider, it can provide an accurate sampling frequency output and support the rate control function and fine-tuning of the output frequency to avoid system problems caused by the cumulative frequency error between different devices.

I2SMCLK

I 2 S Clock

Generator

I2SWS

I2SDO

I2SBCLK

TX FIFO TX Shift Register

APB

Interface

&

Control

Registers

PDMA Req

PDMA Ack

RX FIFO RX Shift Register

Master/Slave

Figure 80. I 2 S Block Diagram

Features

▆

▆

Master or slave mode

Mono and stereo

▆

▆

▆

▆

I 2 S-justified, Left-justified and Right-justified mode

8/16/24/32-bit sample size with 32-bit channel extended

8 × 32-bit TX & RX FIFO with PDMA supported

8-bit Fractional Clock Divider with rate control

I2SDI

Rev. 1.00 339 of 637 December 28, 2020

32-Bit Arm ®

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Cortex ® -M0+ MCU

Functional Description

I

2

S Master and Slave Mode

The I 2 S can operate in slave or master mode. Within the I 2 S module the difference between these modes lies in the word select (WS) signal which determines the timing of data transmissions.

▆

▆

▆

▆

In the master mode, the word select signal is generated internally by a clock rate generator.

In the slave mode, the word select signal is input on the I2S_WS pin.

When an I 2 S bus is enabled, the word select, bit clock signals are sent continuously by the bus master.

The mute control bit will place the transmit channel in a mute condition. When the mute mode is enabled, the transmit channel FIFO operates normally, but the output data stream is discarded and replaced by zeroes. This bit does not affect the receive channel so data reception can occur normally.

I 2 S Master

I2S_BCLK

I2S_WS

I2S_DI

I2S_DO

I2S_BCLK

I2S_WS

I2S_DO

I2S_DI

I 2 S Slave

I 2 S Slave

I2S_BCLK

I2S_WS

I2S_DI

I2S_DO

Figure 81. Simple I 2 S Master/Slave Configuration

Controller

Master

I2S_BCLK

I2S_WS

I2S_DO

I2S_DI

I 2 S Slave

Rev. 1.00 340 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

I

2

S Clock Rate Generator

The main (I2S_MCLK) and bit clock (I2S_BCLK) rates for the I 2 S are determined by the values in the I2SCDR register. The required I 2 S bit clock rate setting depends on the desired audio sample rate desired, the format (stereo/mono) used, and the data size. The main clock rate (I2S_MCLK) is generated using a fractional rate divider which is a divided down PCLK frequency of the I 2 S.

Values of the numerator (X) and the denominator (Y) must be chosen to produce a frequency twice that of the main clock (I2S_MCLK). The output frequency of the divider is divided by 2 in order to get the duty cycle of the output clock more even. The I 2 S clock generator block diagram is shown in

Figure 200. The equation for the fractional rate divider is:

I2S_MCLK = 1/2 × PCLK × (X/Y), and X/Y ≤ 1, X = 1 ~ 255, Y = 1 ~ 255

I2S_BCLK = I2S_MCLK / (N+1), N = 0 ~ 255

Because the fractional rate divider is a fully digital implementation function, the divider output clock transitions are synchronous with the input source clock. Therefore, the fractional rate divider will generate some jitter with some divider settings. Users should make note of this phenomenon when choosing the X and Y setup values. It is possible to avoid jitter entirely by choosing fractions such that X divides evenly into Y. For example, 2/4, 2/6, 3/9, etc.

The tables below show the recommended setup values to reduce clock jitter for different source clocks and sample rates.

PCLK

X Y

8-bit Fractional

Rate Divider

& Fine-Tuning

Controller

I 2 S Clock Generator

2

N

(1 to 64)

I2S_MCLK

I2S_BCLK

I 2 S Control

Logic

I2S_WS

Figure 82. I 2 S Clock Generator Diagram

Rev. 1.00 341 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Table 52. Recommend FS List @ 8 MHz PCLK

Fs (Hz)

8,000

11,025

512 F

S

X

—

Y

—

— —

384 F

S

X

96

256 F

Y X

125 64

S

192 F

Y X

125 48

S

— —

Y

125

170 241 118 223

12,000

16,000

22,050

24,000

32,000

44,100

48,000

96,000

192,000

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

—

96

—

—

—

—

—

125 72

— 96

—

—

—

—

—

—

—

—

—

—

—

—

—

—

125

125

—

—

—

—

—

—

—

128 F

S

X

32

Y

125

90 255

48

64

125

125

170 241

96 125

—

—

—

—

—

—

—

—

—

—

X

16

64 F

S

Y

125

42 238

24

32

90

48

125

125

255

125

64 125

170 241

96 125

—

—

—

—

Table 53. Recommend FS List @ 48 MHz PCLK

Fs (Hz)

8,000

11,025

12,000

512 F

S

X

36

Y

211

4

32

17

125

384 F

S

X

16

256 F

Y X

125 18

S

6

24

34 2

125 16

Y

211

X

8

192 F

S

Y

125

17 6

125 12

68

125

16,000

22,050

24,000

32,000

44,100

48,000

96,000

192,000

86

8

64

252

17

125

32

6

48

125 36

17 4

125 32

142 208 64 125 86

238 253 170 241 8

— — 96 125 64

—

—

—

—

—

—

—

—

—

—

211

17

16

6

125 24

252 32

17 6

125 48

—

—

96

—

125

34

125

125

17

125

125

—

36

4

32

18

2

16

64

—

128 F

S

X

10

Y

234

2

8

34

125

211

17

125

211

17

125

125

—

18

2

16

10

2

8

32

64

2

4

X

2

64 F

S

Y

94

68

125

234

34

125

211

17

125

125

125

Rev. 1.00 342 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

I

2

S Interface Format

I 2 S-justified Stereo Mode

The standard I 2 S-justified mode is where the Most Significant Bit (MSB) of the stereo audio sample data is available on the second rising edge of the BCLK clock following a WS signal transition. In the stereo mode, a low WS state indicates left channel data and a high state indicates right channel data. Figure 83 and Figure 84 show the standard I 2 S-justified stereo mode format.

BCLK

WS

SDO/SDI

Channel Left

MSB

Sample size: 8, 16, 24 or 32-bit

Figure 83. I 2 S-justified Stereo Mode Waveforms

LSB MSB

Channel Right

LSB

32 BCLK cycles mode

BCLK

WS

SDO/SDI MSB

Channel Left

LSB 0 forced or skipped MSB

Channel Right

LSB 0 forced or skipped

Sample size: 8, 16 or 24-bit (32 - Sample size) bits remaining

Figure 84. I 2 S-justified Stereo Mode Waveforms (32-bit Channel Enabled)

Rev. 1.00 343 of 637 December 28, 2020

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Left-justified Stereo Mode

Left-Justified mode is where the Most Significant Bit (MSB) of the stereo audio sample data is available on the first rising edge of BCLK following a WS transition. Figure 85 and Figure 86 are shown with a left I 2 S-justified stereo mode format.

BCLK

WS

SDO/SDI

Channel Left

MSB


Figure 85. Left-justified Stereo Mode Waveforms

LSB MSB

Channel Right

LSB

BCLK

WS

SDO/SDI

Channel Left


Channel Right



Figure 86. Left-justified Stereo Mode Waveforms (32-bit Channel Enabled)

Rev. 1.00 344 of 637 December 28, 2020

32-Bit Arm ®

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Cortex ® -M0+ MCU

Right-justified Stereo Mode

Right-Justified mode is where the Least Significant Bit (LSB) of the stereo audio sample data is available on the rising edge of BCLK preceding a WS transition and where the MSB is transmitted first. Figure 87 and Figure 88 show a right I 2 S-justified stereo mode format.

BCLK

WS

SDO/SDI

Channel Left

MSB


Figure 87. Right-justified Stereo Mode Waveforms

LSB MSB

Channel Right

LSB

BCLK

WS

SDO/SDI

Channel Left

0 forced or skipped MSB

Channel Right


(32 - Sample size) bits remaining

Sample size: 8, 16 or 24-bit

Figure 88. Right-justified Stereo Mode Waveforms (32-bit Channel Enabled)

LSB

Rev. 1.00 345 of 637 December 28, 2020

32-Bit Arm ®

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Cortex ® -M0+ MCU

I 2 S-justified Mono Mode

In the I 2 S-justified mono mode, the Most Significant Bit (MSB) of the mono audio sample data is available on the second rising edge of the BCLK clock following a falling edge on the WS signal.

Figure 89 and Figure 90 show an I 2 S-justified mono mode format.

BCLK

INV

BCLK

WS

SDO/SDI MSB

1 BCLK Sample size: 8, 16, 24 or 32-bit

Figure 89. I 2 S-justified Mono Mode Waveforms

LSB MSB LSB

BCLK

INV

BCLK

WS

SDO/SDI MSB LSB 0 forced or skipped MSB

1 BCLK Sample size: 8, 16 or 24-bit


Figure 90. I 2 S-justified Mono Mode Waveforms (32-bit Channel Enabled)


Rev. 1.00 346 of 637 December 28, 2020

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Cortex ® -M0+ MCU

Left-justified Mono Mode

In the left-justified mono mode, the Most Significant Bit (MSB) of the mono audio sample data is available on the first rising edge of the BCLK clock following a falling edge on the WS signal.

Figure

91 and

Figure

92 show a left-justified mono mode format.

BCLK

INV

BCLK

WS

SDO/SDI MSB

1 BCLK Sample size: 8, 16, 24 or 32-bit

Figure 91. Left-justified Mono Mode Waveforms

LSB MSB LSB

BCLK

INV

BCLK

WS

SDO/SDI MSB LSB 0 forced or skipped MSB

1 BCLK Sample size: 8, 16 or

24-bit


Figure 92. Left-justified Mono Mode Waveforms (32-bit Channel Enabled)


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Right-justified Mono Mode

In the right-justified mono mode, the Least Significant Bit (LSB) of the mono audio sample data is available on the last rising edge of the BCLK clock preceding a rising edge on the WS signal.

Figure 93 and Figure 94 show the right-justified mono mode format.

BCLK

INV

BCLK

WS

SDO/SDI MSB LSB MSB


Figure 93. Right-justified Mono Mode Waveforms

1 BCLK

LSB

BCLK

INV

BCLK

WS

SDO/SDI 0 forced or skipped MSB LSB 0 forced or skipped MSB


Sample size: 8, 16 or

24-bit

1 BCLK

Figure 94. Right-justified Mono Mode Waveforms (32-bit Channel Enabled)

LSB

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I 2 S-justified Repeat Mode

In the I 2 S-justified repeat mode, the Most Significant Bit (MSB) of the mono audio sample data is available on the second rising edge of the BCLK clock following a WS signal transition. In this mode the same data is transmitted twice, once when WS is low and again when WS is high.

Figure

95 and Figure 96 show the I

2 S-justified repeat mode format.

BCLK

WS

SDO/SDI

Mono Sample

MSB


Figure 95. I 2 S-justified Repeat Mode Waveforms repeat sample or skipped

LSB MSB LSB

BCLK

WS

SDO/SDI MSB

Mono Sample

LSB 0 forced or skipped repeat sample or skipped

MSB LSB


Figure 96. I 2 S-justified Repeat Mode Waveforms (32-bit Channel Enabled)

0 forced

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FIFO Control and Arrangement

The I 2 S handles audio data for transmission and reception and is performed via the FIFO controller.

Each transmitted or received FIFO has a depth of 8 words (8 × 32-bit) and can buffer the data. The format is dependent upon the stereo/mono mode and sample size setting. The detailed FIFO data

content format is shown in Figure 97. The FIFO controller consists of comparators which compare

the current FIFO levels with configurable depth settings. The current level of the TX or RX FIFO status can be seen in the TXFS and RXFS fields of the I 2 S status register (I2SSR).

0 7

N+1

0 7

N

0

FIFO Pointer

Address

M

7

Mono 8-bit Data

N+3

0 7

15

Mono 16-bit Data

N+1

Mono 24-bit Data

31 23

Mono 32-bit Data

31

N+2

0 15

N

N

N

0 M

0

M

0 M

7

Stereo 8-bit Data

LEFT+1

0 7

15

Stereo 16-bit Data

LEFT

Stereo 24-bit Data

31 23

RIGHT+1

0 7

0 15

LEFT

LEFT

RIGHT

31

31

Stereo 32-bit Data

23

LEFT

0 7

RIGHT

RIGHT

31

RIGHT

Figure 97. FIFO Data Content Arrangement for Various Modes

0

0

0

0

0

0

M

M

M

M+1

M

M+1

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PDMA and Interrupt

When the level of received data in the RX FIFO is equal to or greater than the level defined by the

RXFTLS field in the I 2 S FIFO control register (I2SFCR), the relative RXFTL flag will be set and then an I 2 S RX PDMA request will be generated. A CPU interrupt will be generated if the enable bit of the I 2 S RX PDMA request or the RX FIFO trigger level interrupt is asserted. When the level of transmitted data in the TX FIFO is equal to or less than the level defined by the TXFTLS field in the I 2 S FIFO control register (I2SFCR), the relative TXFTL flag will be set and an I 2 S TX PDMA request will be generated. A CPU interrupt will be generated if the enable bit of the I 2 S TX PDMA request or TX FIFO trigger level interrupt is asserted.

The I 2 S transmitter and receiver have separate PDMA requests and can be assigned to two different

PDMA channels. When a PDMA request is enabled for the I 2 S transmitter (TXDMAEN = 1) then this will automatically request that data is transferred to the assigned I 2 S TX PDMA channel whenever TX FIFO space is available and TXFTL is active. When a PDMA request is enabled for the receiver (RXDMAEN = 1) then this will automatically request the data transfers to the I

PDMA channel whenever data is present in the receive FIFO and when RXFTL is active.

2 S RX

Register Map

The following table shows the I 2 S registers and reset values.

Table 54. I 2 S Register Map

Register Offset

I2SCR

I2SIER

I2SCDR

I2STXDR

0x000

0x004

0x008

0x00C

I2SRXDR

I2SFCR

I2SSR

I2SRCNTR

0x010

0x014

0x018

0x01C

Description

I 2 S Control Register

I 2 S Interrupt Enable Register

I 2 S Clock Divider Register

I 2 S TX Data Register

I 2 S RX Data Register

I 2 S FIFO Control Register

I 2 S Status Register

I 2 S Rate Counter Value Register

Reset Value

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0809

0x0000_0000

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I

2

S Control Register – I2SCR

This register specifies the corresponding I 2 S function enable control.

Offset: 0x000


31 30 29 28 27

Reserved

26 25 24

Type/Reset

Type/Reset

23 22 21

Reserved

20 19 18

MCKINV BCKINV

17

RCSEL

16

RCEN

RW 0 RW 0 RW 0 RW 0

15 14 13 12 11 10 9 8

CLKDEN RXDMAEN TXDMAEN TXMUTE CHANNEL REPEAT MCLKEN BITEXT


7 6 5 4 3 2 1 0

FORMAT SMPSIZE MS RXEN TXEN I2SEN


Bits

[19]

[18]

[17]

[16]

[15]

[14]

[13]

[12]

Field

MCKINV

BCKINV

Descriptions

MCLK Inverse Enable

0: Disable

1: Enable

BCLK Inverse Enable

0: Disable

1: Enable

RCSEL

RCEN

Rate Control Select (master only)

0: slower

1: faster

Rate Control Enable (master only)

0: Disable

1: Enable

CLKDEN Clock Divider Enable (master only)

0: Disable

1: Enable

The clock divider can be used to generate the MCLK and BCLK clock of the I interface for master mode.

2 S

RXDMAEN RX PDMA Request Enable

0: Disable

1: Enable

TXDMAEN TX PDMA Request Enable

0: Disable

1: Enable

TXMUTE TX Mute Enable

0: Disable

1: Enable

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[9]

[8]

[3]

[2]

[1]

[0]

Bits

[11]

[10]

[7:6]

[5:4]

Field

CHANNEL

REPEAT

MCLKEN

BITEXT

FORMAT

SMPSIZE

MS

RXEN

TXEN

I2SEN

Descriptions

Stereo or Mono

0: Stereo

1: Mono

Note: This bit should be configured when I 2 S is disabled.

Repeat Mode

0: Disable

1: Enable

This mode is for I 2 S-justified stereo configuration only, transmitting the mono data on both channels and receiving just the left channel data and ignoring the right. The repeat mode is only available when the CHANNEL is configured to select Stereo.

Note: This bit should be configured when the I 2 S is disabled.

MCLK Output Enable (master only)

0: Disable

1: Enable


32-bit Channel Enable

0: Disable

1: Enable

Setting this bit will force the channel size to 32-bits. If the sample size is 8/16/24bits, the remaining bits will be forced to 0 in the TX and ignored in the RX.


Data Format

00: I 2 S-justified

01: Left-justified

10: Right-justified

11: reserved


Sample Size

00: 8-bit

01: 16-bit

10: 24-bit

11: 32-bit


Master or Slave Mode

0: Master

1: Slave


RX Enable

0: Disable

1: Enable

TX Enable

0: Disable

1: Enable

I 2 S Enable

0: Disable

1: Enable

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I

2

S Interrupt Enable Register – I2SIER

This register contains the corresponding I 2 S interrupt enable bits.

Offset: 0x004


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

Type/Reset

Type/Reset

15 14 13 12 11

Reserved

10 9 8

7 6 5 4 3 2 1 0

Reserved RXOVIEN RXUDIEN RXFTLIEN Reserved TXOVIEN TXUDIEN TXFTLIEN


Bits

[6]

[5]

[4]

[2]

[1]

[0]

Field

RXOVIEN

RXUDIEN

RXFTLIEN

TXOVIEN

TXUDIEN

TXFTLIEN

Descriptions

RX FIFO Overflow Interrupt Enable

0: Disable

1: Enable

RX FIFO Underflow Interrupt Enable

0: Disable

1: Enable

RX FIFO Trigger Level Interrupt Enable

0: Disable

1: Enable

TX FIFO Overflow Interrupt Enable

0: Disable

1: Enable

TX FIFO Underflow Interrupt Enable

0: Disable

1: Enable

TX FIFO Trigger Level Interrupt Enable

0: Disable

1: Enable

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I

2

S Clock Divider Register – I2SCDR

This register specifics the I 2 S clock divider ratio.

Offset: 0x008


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

N_DIV

18 17 16


15 14 13 12 11

X_DIV

10 9 8


7 6 5 4 3 2 1 0

Y_DIV


Bits

[23:16]

[15:8]

[7:0]

Field

N_DIV

X_DIV

Y_DIV

Descriptions

N divider for BCLK

0x00: divide 1

0x01: divide 2

...

0xFF: divide 256


X divider for MCLK

(X = 1 ~ 255) && (X / Y ≤ 1)


Y divider for MCLK

(Y = 1 ~ 255) && (X / Y ≤ 1)


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I

2

S TX Data Register – I2STXDR

This register is used to specify the I 2 S transmitted data.

Offset: 0x00C


31 30 29 28 27

TXDR

26 25 24

Type/Reset WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0 WO 0

23 22 21 20 19

TXDR

18 17 16


15 14 13 12 11

TXDR

10 9 8


7 6 5 4 3 2 1 0

TXDR


Bits

[31:0]

Field

TXDR

Descriptions

TX Data Register

I

2

S RX Data Register – I2SRXDR

This register is used to store the I 2 S received data.

Offset: 0x010


31 30 29 28 27

RXDR

26 25 24


23 22 21 20 19 18 17 16

RXDR


15 14 13 12 11

RXDR

10 9 8


7 6 5 4 3 2 1 0

RXDR


Bits

[31:0]

Field

RXDR

Descriptions

RX Data Register

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Bits

[9]

[8]

[7:4]

I

2

S FIFO Control Register – I2SFCR

This register contains the related I 2 S FIFO control bits.

Offset: 0x014


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12

Reserved

11 10 9 8

RXFRST TXFRST

Type/Reset

7 6 5

RXFTLS

4 3 2

RW 0 RW 0

1

TXFTLS

0


[3:0]

Field

RXFRST

TXFRST

RXFTLS

TXFTLS

Descriptions

RX FIFO Reset

Set this bit to reset the RX FIFO.

TX FIFO Reset

Set this bit to reset the TX FIFO.

RX FIFO Trigger Level Select

0000: Trigger level is 0


...


1xxx: Trigger level is 8

When the data contained in the RX FIFO is equal to or greater than the level defined by the RXFTLS field, the RXFTL flag will be set.

TX FIFO Trigger Level Select



...


1xxx: Trigger level is 8

When the data contained in the TX FIFO is equal to or less than the level defined by the TXFTLS field, the TXFTL flag will be set.

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I

2

S Status Register – I2SSR

This register contains the relevant I 2 S status.

Offset: 0x018


31 30 29

RXFS

28 27 26 25

TXFS

24


Type/Reset

23 22 21

Reserved

20 19 18 17

CLKRDY TXBUSY

16

CHS

RO 0 RO 0 RO 0

Type/Reset

Type/Reset

15

7

14

Reserved

6

Reserved

13

5

12 11 10

RXFFUL RXFEMT RXFOV

9

RXFUD

8

RXFTL

RO 0 RO 1 WC 0 WC 0 WC 0

4 3 2 1 0

TXFFUL TXFEMT TXFOV TXFUD TXFTL

RO 0 RO 1 WC 0 WC 0 WC 1

Bits

[31:28]

[27:24]

[18]

[17]

[16]

[12]

[11]

Field

RXFS

TXFS

CLKRDY

TXBUSY

CHS

RXFFUL

RXFEMT

Descriptions

RX FIFO Status

0000: RX FIFO empty

0001: RX FIFO contains 1 data

...

1000: RX FIFO contains 8 data

Others: Reserved

TX FIFO Status

0000: TX FIFO empty

0001: TX FIFO contains 1 data

…

1000: TX FIFO contains 8 data

Others: Reserved

Clock Divider Output Ready Flag

0: not ready

1: ready

TX Busy Flag

0: not busy

1: busy

Channel Status

0: left channel

1: right channel

RX FIFO Full Flag

0: RX FIFO not full

1: RX FIFO full

RX FIFO Empty Flag

0: RX FIFO not empty

1: RX FIFO empty

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Bits

[10]

[9]

[8]

[4]

[3]

[2]

[1]

[0]

Field

RXFOV

RXFUD

RXFTL

TXFFUL

TXFEMT

TXFOV

TXFUD

TXFTL

Descriptions

RX FIFO Overflow Flag

0: RX FIFO not overflow

1: RX FIFO overflow

This bit is set by hardware and cleared by writing 1.

RX FIFO Underflow Flag

0: RX FIFO not underflow

1: RX FIFO underflow


RX FIFO Trigger Level Flag

0: Data in the RX FIFO is less than the trigger level

1: Data in the RX FIFO is equal to or higher than the trigger level


TX FIFO Full Flag

0: TX FIFO not full

1: TX FIFO full

TX FIFO Empty Flag

0: TX FIFO not empty

1: TX FIFO empty

TX FIFO Overflow Flag

0: TX FIFO not overflow

1: TX FIFO overflow


TX FIFO Underflow Flag

0: TX FIFO not underflow

1: TX FIFO underflow


TX FIFO Trigger Level Flag

0: Data in the TX FIFO is higher than the trigger level

1: Data in the TX FIFO is equal to or less than the trigger level


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I

2

S Rate Counter Value Register – I2SRCNTR

This register specifics the I 2 S rate control counter value.

Offset: 0x01C


31 30 29 28 27

Reserved

26 25 24

Type/Reset

Type/Reset

23 22 21

Reserved

20 19 18 17

RCNTR

16

RW 0 RW 0 RW 0 RW 0

15 14 13 12 11

RCNTR

10 9 8


7 6 5 4 3 2 1 0

RCNTR


Bits

[19:0]

Field

RCNTR

Descriptions

Rate Counter Value

This value must be higher than zero for useful rate fine-tuning control.

RCSEL = 1, RCNTR = 1 ~ (2Y-1): MCLK' = (1 +

RCSEL = 1, RCNTR > (2Y-1): MCLK' = (1 +

(2Y-1) )

1

1

× MCLK

RCNTR )

× MCLK

RCSEL = X, RCNTR = 0: MCLK' = MCLK

RCSEL = 0, RCNTR > (2Y+1): MCLK' = (1 +

1

RCNTR )

RCSEL = 0, RCNTR = 1 ~ (2Y+1): MCLK' = (1 +

1

2Y+1 )

× MCLK

× MCLK

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19

Analog to Digital Converter (ADC)

Introduction

A 12-bit multi-channel Analog to Digital Converter (ADC) with a Voltage Reference Generator

(V

REF

) is integrated in the device. There are a total of 16 multiplexed channels including 10 external channels on which the external analog signal can be supplied and 6 internal channels. If the input voltage is required to remain within a specific threshold window, the Analog Watchdog function will monitor and detect the signal. An interrupt will then be generated to inform that the input voltage is higher or lower than the set thresholds. There are three conversion modes to convert an analog signal to digital data. The A/D conversion can be operated in one shot, continuous and discontinuous conversion mode. A 16-bit data register is provided to store the data after conversion.

ADC_IN0

ADC_IN1

ADC_IN9

VDDA

Up to 16 Channels

MVDDAEN

From ADC Prescaler

CK_ADC

V

DDA

DAC1O

DAC0O

V

REF

V

MV

SSA

DDA

0

1

9

12

13

14

15

16

17

ADCIN

12-bit A/D

Converter

VDDA

VREF+

VSSA

R

MV

DDA

R

Voltage Reference Generator (V

VREFEN

Bandgap

REF

)

VREF-

VSSA

V

REF

PA0

AFIO15

ADCTCR[4:0]

ADC Control Logic

Analog Watchdog

High Threshold

Low Threshold

Analog Watchdog Event

Analog Watchdog

Interrupt

ADCTSR[31:0]

Start Trigger

DMA Request

EOC OV

Interrupt

Generator ADC Interrupt to NVIC

VREFVAL[6:0]

VREFSEL[1:0]

PA0

Figure 98. ADC with V

REF

Block Diagram

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Features

▆

▆

▆

▆

▆

▆

▆

▆

▆

▆

▆

▆

▆

12-bit SAR ADC engine

Up to 1 Msps conversion rate

Up to 10 external analog input channels

1 channel for internal voltage reference (V

REF

)

2 channels for monitor external V

DDA

power support pin

2 channels for internal DAC output

Programmable sampling time for conversion channel

Up to 8 programmable conversion channel sequence and dedicated data registers for conversion result

Three conversion mode

● One shot conversion mode

● Continuous conversion mode

● Discontinuous conversion mode

Analog watchdog for predefined voltage range monitor

● Lower/upper threshold register

● Interrupt generation

Various trigger start sources for conversion modes

● Software trigger

●

● GPTM trigger

●

EXTI – external interrupt input pin

PWM0 / PWM1 trigger

● BFTM0 / BFTM1 trigger

● CMP0 / CMP1 trigger

Multiple generated interrupts

● End of single conversion

●

● End of cycle conversion

●

End of subgroup conversion

Analog Watchdog

● Data register overwriting

PDMA request on end of conversion occurred

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ADC Clock Setup

The ADC clock, CK_ADC is provided by the Clock Controller which is synchronous and divided by with the AHB clock known as HCLK. Refer to the Clock Control Unit chapter for more details.

Notes that the ADC requires at least two ADC clock cycles to switch between power-on and poweroff conditions (ADEN bit = ‘0’).

Channel Selection

The A/D converter supports 16 multiplexed channels and organizes the conversion results into a specific group. A conversion group can organize a sequence which can be implemented on the channels arranged in a specific conversion sequence length from 1 to 8. For example, conversion can be carried out with the following channel sequence: CH2, CH4, CH7, CH5, CH6, CH3, CH0 and CH1 one after another.

A group is composed of up to 8 conversions. The selected channels of the group conversion can be specified in the ADCLST0 ~ ADCLST1 registers. The total conversion sequence length is setup using the ADSEQL[2:0] bits in the ADCCR register.

Modifying the ADCCR register during a conversion process will reset the current conversion, after which a new start pulse is required to restart a new conversion.

Conversion Mode

The A/D has three operating conversion modes. The conversion modes are One Shot Conversion

Mode, Continuous Conversion Mode, and Discontinuous Conversion mode. Details are provided later.

One Shot Conversion Mode

In the One Shot Conversion mode, the ADC will perform conversion cycles on the channels specified in the A/D conversion list registers ADCLSTn with a specific sequence when an A/D converter trigger event occurs. When the A/D conversion mode field ADMODE [1:0] in the

ADCCR register is set to 0x0, the A/D converter will operate in the One Shot Conversion Mode.

This mode can be started by a software trigger, a comparator output transition event, an external

EXTI event or a TM event determined by the Trigger Control Register ADCTCR and the Trigger

Source Register ADCTSR.

After Conversion:

▆

The converted data will be stored in the 16-bit ADCDRy (y = 0 ~ 7) registers.

▆

The ADC single sample end of conversion event raw status flag, ADIRAWS, in the ADCIRAW register will be set when the single sample conversion is finished.

▆

▆

An interrupt will be generated after a single sample end of conversion if the ADIES bit in the

ADCIER register is enabled.

An interrupt will be generated after a group cycle end of conversion if the ADIEC bit in the


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Conversion (ex: Sequence Length=8)

Cycle

CH2 CH4 CH7 CH5 CH6 CH3 CH0 CH1

Start of

Conversion

Single sample

End of

Conversion

Cycle End of

Conversion

Figure 99. One Shot Conversion Mode

Cycle

CH2 CH4 CH7 CH5 CH6

Continuous Conversion Mode

In the Continuous Conversion Mode, repeated conversion cycle will restart automatically without requiring additional A/D start trigger signals after a channel group conversion has completed.

When the A/D conversion mode field ADMODE[1:0] is set to 0x2, the A/D converter will operate in the Continuous Conversion Mode which can be started by a software trigger, a comparator output transition event, an external EXTI event or a TM event determined by the Trigger Control

Register ADCTCR and the Trigger Source Register ADCTSR.

After conversion:

▆

The converted data will be stored in the 16-bit ADCDRy (y = 0 ~ 7) registers.

▆

▆

The ADC group cycle end of conversion event raw status flag, ADIRAWC, in the ADCIRAW register will be set when the conversion cycle is finished.

An interrupt will be generated after a group cycle end of conversion if the ADIEC bit in the


Continuous Conversion Mode

(ex: Sequence Length=8)

Idle

Cycle Cycle

CH2 CH4 CH7 CH5 CH6 CH3 CH0 CH1 CH2 CH4 CH7 CH1

Start of Conversion

Single sample End of

Conversion

Cycle End of Conversion

Figure 100. Continuous Conversion Mode

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Discontinuous Conversion Mode

The A/D converter will operate in the Discontinuous Conversion Mode for channels group when the A/D conversion mode bit field ADMODE [1:0] in the ADCCR register is set to 0x3.

The group to be converted can have up to 8 channels and can be arranged in a specific sequence by configuring the ADCLSTn registers where n ranges from 0 to 1. This mode is provided to convert data for the group with a short sequence, named as the A/D conversion subgroup, each time a trigger event occurs. The subgroup length is defined by the ADSUBL [2:0] field in the

ADCCR register to specify the subgroup length. In the Discontinuous Conversion Mode the A/D converter can be started by a software trigger, a comparator output transition event, an external

EXTI event or a TM event for the groups determined by the Trigger Control Register ADCTCR and the Trigger Source Register ADCTSR.

In the Discontinuous Conversion Mode, the A/D Converter will start to convert the next n conversions where the number n is the subgroup length defined by the ADSUBL field. When a trigger event occurs, the channels to be converted with a specific sequence are specified in the

ADCLSTn registers. After n conversions have completed, the subgroup EOC interrupt raw flag

ADIRAWG in the ADCIRAW register will be asserted. The A/D converter will now not continue to perform the next n conversions until the next trigger event occurs. The conversion cycle will end after all the group channels, of which the total number is defined by the ADSEQL[2:0] bits in the

ADCCR register, have finished their conversion, at which point the cycle EOC interrupt raw flag

ADIRAWC in the ADCIRAW register will be asserted. If a new trigger event occurs after all the subgroup channels have all been converted, i.e., a complete conversion cycle has been finished, the conversion will restart from the first subgroup.

Example:

A/D subgroup length = 3 (ADSUBL = 2) and sequence length = 8 (ADSEQL = 7), channels to be converted = 2, 4, 7, 5, 6, 3, 0 and 1 – specific converting sequence as defined in the ADCLSTn registers,

▆

▆

▆

▆

Trigger 1: subgroup channels to be converted are CH2, CH4 and CH7 with the ADIRAWG flag being asserted after subgroup EOC.

Trigger 2: subgroup channels to be converted are CH5, CH6 and CH3 with the ADIRAWG flag being asserted after subgroup EOC.

Trigger 3: subgroup channels to be converted are CH0 and CH1 with the ADIRAWG flag being asserted after subgroup EOC. Also a Cycle end of conversion (EOC) interrupt raw flag

ADIRAWC will be asserted.

Trigger 4: subgroup channels to be converted are CH2, CH4 and CH7 with the ADIRAWG flag being asserted - conversion sequence restarts from the beginning.

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Discontinuous Conversion Mode

(ex: Sequence Length=8, Subgroup Length=3 )

Cycle

CH2 CH4 CH7 CH5 CH6 CH3

Subgroup 0 Subgroup 1

Start of

Conversion

Single sample

End of

Conversion

Subgroup End of Conversion

Cycle End of

Conversion

Figure 101. Discontinuous Conversion Mode

CH0 CH1

Subgroup 2

Cycle

CH2 CH4 CH7

Subgroup 0

Start Conversion on External Event

An A/D conversion can be initiated by a software trigger, a comparator output transition event, a General-Purpose Timer Module (GPTM) event, a Pulse Width Modulator (PWM) event, a

Basic Function Timer Module (BFTM) event or an external trigger. Each trigger source can be enabled by setting the corresponding enable control bit in the ADCTCR register and then selected by configuring the associated selection bits in the ADCTSR register to start a group channel conversion.

An A/D conversion can be started by setting the software trigger bit, ADSC, in the ADCTSR register for the group channel when the software trigger enable bit, ADSW, in the ADCTCR register is set to 1. After the A/D converter starts converting the analog data, the corresponding enable bit ADSC will be cleared to 0 automatically.

The A/D converter can also be triggered to start a group conversion by a TM event. The TM events include a GPTM or PWM master trigger output MTO, four GPTM or PWM channel outputs CH0

~ CH3 and a BFTM trigger output. If the corresponding Timer trigger enable bit is set to 1 and the trigger output or the TM channel event is selected via the relevant TM event selection bits, the A/D converter will start a conversion when a rising edge of the selected trigger event occurs.

In addition to the internal trigger sources, the A/D converter can be triggered to start a conversion by an external trigger event. The external trigger event is derived from the external lines of the

EXTI unit. If the external trigger enable bit ADEXTI is set to 1 and the corresponding EXTI line is selected by configuring the ADEXTIS field in the ADCTSR register, the A/D converter will start a conversion when an EXTI line active edge determined in the EXTI Unit occurs.

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Sampling Time Setting

The conversion channel sampling time can be programmed according to the input resistance of the input voltage source. This sampling time must be enough for the input voltage source to charge the internal sample and hold capacitor in the A/D converter to the input voltage level. Each conversion channel is sampled with the same sampling time. By modifying the ADST[7:0] bits in the ADCSTR register, the sampling time of the analog input signal can be determined.

The total conversion time (T conv

) is calculated using the following formula:

T conv

= T

Sampling

+ T

Latency

Where the minimum sampling time T

Sampling channel conversion latency T

Latency

= 1.5 cycles (when ADST[7:0] = 0) and the minimum

= 12.5 cycles.

Example:

With the A/D Converter clock CK_ADC = 14 MHz and a sampling time = 1.5 cycles:

T conv

= 1.5 + 12.5 = 14 cycles = 1 μs

Data Format

The ADC conversion result can be read in the ADCDRy register and the data format is shown in

the following table.

Table 55. Data format in ADCDR [15:0]

Description

Right aligned

ADCDR register Data Format

“0_0_0_0_d11_d10_d9_d8_d7_d6_d5_d4_d3_d2_d1_d0”

Analog Watchdog

The A/D converter includes a watchdog function to monitor the converted data. There are two kinds of thresholds for the watchdog monitor function, known as the watchdog lower threshold and watchdog upper threshold, which are specified by the ADLT bit field and ADUT bit field in the

ADCTR register respectively. The watchdog monitor function is enabled by setting the watchdog upper and lower threshold monitor function enable bits, ADWUE and ADWLE, in the watchdog control register ADCWCR. The channel to be monitored can be specified by configuring the

ADWCH and ADWALL bits. When the converted data is less or higher than the lower or upper threshold, as defined by the ADLT bit field and ADUT bit field in the ADCTR register respectively, the watchdog lower or upper threshold interrupt raw flags, ADIRAWL or ADIRAWU in the

ADCIRAW register, will be asserted if the watchdog lower or upper threshold monitor function is enabled. If the lower or upper threshold interrupt raw flag is asserted and the corresponding interrupt is enabled by setting the ADIEL or ADIEU bit in the ADCIER register, the A/D watchdog lower or upper threshold interrupt will be generated.

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Interrupts

When an A/D conversion is completed, an End of Conversion EOC event will occur. There are three types of EOC events which are known as single sample EOC, subgroup EOC and cycle EOC for A/D conversion. A single sample EOC event will occur and the single sample EOC interrupt raw flag, ADIRAWS bit in the ADCIRAW register, will be asserted when a single channel conversion has completed. A subgroup EOC event will occur and the subgroup EOC interrupt raw flag, ADIRAWG in the ADCIRAW register, will be asserted when a subgroup conversion has completed. A cycle EOC event will occur and the cycle EOC interrupt raw flag, ADIRAWC bits in the ADCIRAW register, will be asserted when a cycle conversion is finished. When a single sample

EOC, a subgroup EOC or a cycle EOC raw flag is asserted and the corresponding interrupt enable bit, ADIES, ADIEG or ADIEC bit in the ADCIER register, is set to 1, the associated interrupt will be generated.

After a conversion has completed, the 12-bit digital data will be stored in the associated ADCDRy registers and the value of the data valid flag named as ADVLDy will be changed from low to high.

The converted data should be read by the application program, after which the data valid flag

ADVLDy will be automatically changed from high to low. Otherwise, a data overwrite event will occur and the data overwrite interrupt raw flag ADIRAWO bit in the ADCIRAW register will be asserted. When the related data overwrite raw flag is asserted, the data overwrite interrupt will be generated if the interrupt enable bit ADIEO in the ADCIER register is set to 1.

If the A/D watchdog monitor function is enabled and the data after a channel conversion is less than the lower threshold or higher than the upper threshold, the watchdog lower or upper threshold interrupt raw flag ADIRAWL or ADIRAWU in the ADCIRAW register will be asserted. When the ADIRAWL or ADIRAWU flag is asserted and the corresponding interrupt enable bit, ADIEL or ADIEU in the

ADCIER register, is set a watchdog lower or upper threshold interrupt will be generated.

The A/D Converter interrupt clear bits are used to clear the associated A/D converter interrupt raw and interrupt status bits. Writing a 1 into the specific A/D converter interrupt clear bit in the A/D converter interrupt clear register ADCICLR will clear the corresponding A/D converter interrupt raw and interrupt status bits. These bits are automatically cleared to 0 by hardware after being set to 1.

PDMA Request

The converted channel value will be stored in the corresponding data register. The A/D Converter can inform the MCU using the A/D Converter EOC interrupt if a new conversion data is already stored in the ADCDRy register. Users also can determine if the PDMA request is asserted by setting the ADDMAC, ADDMAG or ADDMAS bits in the ADCDMAR register. A PDMA request will be automatically generated at the relevant end of A/D conversion. The detail description will be introduced in the ADCDMAR register description.

Voltage Reference Generator

The internal voltage reference generator (V

REF

Comparators. The V

REF the V

REF

) provides a stable voltage output for the ADC and

is internally connected to the ADC input channel. The precise voltage of

is individually measured and calculated for each part by manufacture during production test and stored in the Flash Manufacture Privilege Information Block. It can be accessed using the VREFVALR register in the read-only mode. Refer to the datasheet for additional information.

When not in use or using the external voltage reference from the VREF pin, the internal V

REF generator can be configured in the power down mode to save power consumption.

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Voltage Reference Generator (V

REF

)

VREFEN

V

DDA

VREFVAL[6:0]

Bandgap

VREFSEL[1:0]

Figure 102. Voltage Reference Generator Block Diagram

V

REF

PA0

AFIO15

PA0

V

DDA

Voltage Monitor

The MVDDAEN bit in the VREFCR register allows the application to measure the V on the VDDA pin. As the V

DDA

DDA

voltage

voltage could be higher than the ADC reference voltage, in order to ensure the correct operation of the ADC, the VDDA pin is internally connected to a bridge divider by 2. This bridge is automatically enabled when the MVDDAEN bit is set, to connect the V the ADC input channel. As a consequence, the converted digital value is half of the V

DDA

To prevent any unwanted consumption on the battery, it is recommended to enable the V

DDA divider only when the ADC conversion is required

DDA

/2 to

voltage.

power

Register Map

The following table shows the A/D Converter registers and reset values.

Table 56. A/D Converter Register Map

Register

ADCCR

Offset

0x000

Description

ADC Conversion Control Register

ADCLST0 0x004

ADCLST1 0x008

ADCSTR

ADCDR0

ADCDR1

0x020

0x030

0x034

ADCDR2

ADCDR3

ADCDR4

ADCDR5

0x038

0x03C

0x040

0x044

ADCDR6

ADCDR7

ADCTCR

ADCTSR

0x048

0x04C

0x070

0x074

ADCWCR 0x078

ADCTR 0x07C

ADCIER 0x080

ADCIRAW 0x084

ADCISR 0x088

ADCICLR 0x08C

ADCDMAR 0x090

VREFCR 0x0A0

VREFVALR 0x0A4

ADC Conversion List Register 0

ADC Conversion List Register 1

ADC Input Sampling Time Register

ADC Conversion Data Register 0








ADC Trigger Control Register

ADC Trigger Source Register

ADC Watchdog Control Register

ADC Watchdog Threshold Register

ADC Interrupt Enable register

ADC Interrupt Raw Status Register

ADC Interrupt Status Register

ADC Interrupt Clear Register

ADC DMA Request Register

Voltage Reference Control Register

Voltage Reference Value Register

Reset Value

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_00XX

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ADC Conversion Control Register – ADCCR

This register specifies the mode setting, sequence length and subgroup length of the ADC conversion mode.

Note that once the content of ADCCR is changed, the conversion in progress will be aborted and the A/D converter will return to an idle state. The application program has to wait for at least one CK_ADC clock before issuing the next command.

Offset: 0x000


31 30 29 28

Type/Reset

23 22 21

Reserved

Type/Reset

15 14

Type/Reset

7 6

ADCEN ADCRST


13

Reserved

5

20

12

4

Reserved

27

Reserved

19

11

3

26 25 24

18 17

ADSUBL

16

RW 0 RW 0 RW 0

10 9

ADSEQL

8

RW 0 RW 0 RW 0

2 1 0

ADMODE

RW 0 RW 0

Bits

[18:16]

[10:8]

[7]

[6]

Field

ADSUBL

ADSEQL

ADCEN

ADCRST

Descriptions

ADC Conversion Subgroup Length

The ADSUBL field specifies the conversion channel length of each subgroup in the Discontinuous Conversion Mode. Subgroup length = ADSUBL [2:0] + 1. If the sequence length (ADSEQL [2:0] + 1) is not a multiple of the subgroup length

(ADSUBL [2:0] + 1), the last subgroup will be the rest of the group channels that have not been converted.

ADC Conversion Length

0x00: The channel specified by the ADSEQ0 field in the ADCLST0 register will be converted

Others: Sequence length = ADSEQL [2:0] + 1

The ADSEQL field specifies the whole conversion sequence length for the conversion group.

ADC Enable

0: ADC is disabled

1: ADC is enabled

When this bit is cleared to 0, the A/D converter will be disabled and the CK_ADC clock will also be switched off.

ADC Reset

0: No effect

1: Reset A/D converter except for the A/D converter controller

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Bits

[1:0]


ADMODE ADC Conversion Mode

ADMODE [1:0]

00

01

10

11

Mode

One shot mode

Descriptions

After a start trigger, the conversion will be executed on the specific channels for the whole conversion sequence once.

Reserved

Continuous mode

Discontinuous mode

After a start trigger, the conversion will be executed on the specific channels for the whole sequence continuously until conversion mode is changed.

After a start trigger, the conversion will be executed on the current subgroup. When the last subgroup is finished, the conversion will restart from the first subgroup if another start trigger occurs.

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ADC Conversion List Register 0 – ADCLST0

This register specifies the conversion sequence order No.0 ~ No.3 of the ADC.

Offset: 0x004


Type/Reset

Type/Reset

Type/Reset

Type/Reset

31

23

15

7

30

Reserved

22

Reserved

14

Reserved

6

Reserved

29

21

13

5

28 27 26

ADSEQ3

25 24

RW 0 RW 0 RW 0 RW 0 RW 0

20 19 18

ADSEQ2

17 16


12 11 10

ADSEQ1

9 8


4 3 2 1 0

ADSEQ0


Bits

[28:24]

[20:16]

[12:8]

[4:0]

Field

ADSEQ3

ADSEQ2

ADSEQ1

ADSEQ0

Descriptions

ADC Conversion Sequence Select 3

Select the ADC input channel for the 3 rd ADC conversion sequence.

0x0: ADC_IN0

0x1: ADC_IN1

0x2: ADC_IN2

0x3: ADC_IN3

0x4: ADC_IN4

0x5: ADC_IN5

0x6: ADC_IN6

0x7: ADC_IN7

0x8: ADC_IN8

0x9: ADC_IN9

0xA~0xB: Reserved

0xC: V

DDA

0xD: DAC1O

0xE: DAC0O

0xF: Internal Voltage Reference (V

0x10: Analog ground V

SSA

0x11: Analog power MV

DDA

(V

DDA

/2)

REF

)

0x12 ~ 0x1F: Invalid setting. These values must not be selected as it may cause the ADC abnormal operations.




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ADC Conversion List Register 1 – ADCLST1

This register specifies the conversion sequence order No.4 ~ No.7 of the ADC.

Offset: 0x008


Type/Reset

Type/Reset

Type/Reset

Type/Reset

31

23

15

7

30

Reserved

22

Reserved

14

Reserved

6

Reserved

29

21

13

5

28 27 26

ADSEQ7

25 24


20 19 18

ADSEQ6

17 16


12 11 10

ADSEQ5

9 8


4 3 2 1 0

ADSEQ4


Bits

[28:24]

[20:16]

[12:8]

[4:0]

Field

ADSEQ7

ADSEQ6

ADSEQ5

ADSEQ4

Descriptions


Select the ADC input channel for the 7 th ADC conversion sequence.

0x0: ADC_IN0

0x1: ADC_IN1

0x2: ADC_IN2

0x3: ADC_IN3

0x4: ADC_IN4

0x5: ADC_IN5

0x6: ADC_IN6

0x7: ADC_IN7

0x8: ADC_IN8

0x9: ADC_IN9

0xA~0xB: Reserved

0xC: V

DDA

0xD: DAC1O

0xE: DAC0O

0xF: Internal Voltage Reference (V

0x10: Analog ground V

SSA

0x11: Analog power MV

DDA

(V

DDA

/2)

REF

)

0x12 ~ 0x1F: Invalid setting. These values must not be selected as it may cause the ADC abnormal operations.




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ADC Input Sampling Time Register – ADCSTR

This register specifies the A/D converter input channel sampling time.

Offset: 0x020


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

Reserved

10 9 8

Type/Reset

7 6 5 4 3

ADST

2 1 0


Bits

[7:0]

Field

ADST

Descriptions

ADC Input Channel Sampling Time

Sampling time = (ADST[7:0] + 1.5) × CK_ADC clocks.

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ADC Conversion Data Register y – ADCDRy, y = 0 ~ 7

This register is used to store the conversion data of the conversion sequence order No.y which is specified by the ADSEQy field in the ADCLSTn (n = 0 ~ 1) registers.

Offset: 0x030 ~ 0x04C


31

ADVLDy

Type/Reset RC 0

23

30 29 28 27

Reserved

26 25 24

22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

ADDy

10 9 8


7 6 5 4 3 2 1 0

ADDy


Bits

[31]

[15:0]

Field

ADVLDy

ADDy

Descriptions

ADC Conversion Data of Sequence Order No.y Valid Bit (y = 0 ~ 7)

0: Data are invalid or have been read

1: New data is valid

ADC Conversion Data of Sequence Order No.y (y = 0 ~ 7)

The conversion result of Sequence Order ADSEQy in the ADCLSTn (n = 0 ~ 1) registers

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ADC Trigger Control Register – ADCTCR

This register contains the ADC start conversion trigger enable bits.

Offset: 0x070


31 30 29

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

Reserved

21

13

5

28

20

27

Reserved

19

Reserved

26

18

25

17

24

16

12 11

Reserved

10 9 8

4

CMP

3

TM1

2

TM0

1

ADEXTI

0

ADSW


Bits

[4]

[3]

[2]

[1]

[0]

Field

CMP

TM1

TM0

ADEXTI

ADSW

Descriptions

ADC Conversion CMP Event Trigger enable control

0: Disable conversion trigger by CMP output transition

1: Enable conversion trigger by CMP output transition

ADC Conversion BFTM or PWM Event Trigger enable control

0: Disable conversion trigger by BFTM or PWM events

1: Enable conversion trigger by BFTM or PWM events

ADC Conversion GPTM Event Trigger enable control

0: Disable conversion trigger by GPTM events

1: Enable conversion trigger by GPTM events

ADC Conversion EXTI Event Trigger enable control

0: Disable conversion trigger by EXTI lines

1: Enable conversion trigger by EXTI lines

ADC Conversion Software Trigger enable control

0: Disable conversion trigger by software trigger bit

1: Enable conversion trigger by software trigger bit

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ADC Trigger Source Register – ADCTSR

This register contains the trigger source selection and the software trigger bit of the conversion.

Offset: 0x074


Type/Reset

31 30

Reserved

29 28

TM1E

27 26 25

TM0E

24


23 22 21

TM1S[2:1] Reserved


Type/Reset

Type/Reset

15

7

14

6

13

Reserved

5

20

CMPS

12

4

Reserved

19

TM1S[0]


11

18

10

17

TM0S

9

ADEXTIS

16

8

RW 0 RW 0 RW 0 RW 0

3 2 1 0

ADSC

RW 0

Bits

[29:27]

[26:24]

[20]

[23:22],

[19]

[18:16]

Field

TM1E

TM0E

CMPS

TM1S

TM0S

Descriptions

PWM Trigger Event Selection of ADC Conversion

000: PWM MTO event

001: PWM CH0O event

010: PWM CH1O event

011: PWM CH2O event

100: PWM CH3O event

Others: Reserved -- Should not be used to avoid unpredictable results

GPTM Trigger Event Selection of ADC Conversion

000: GPTM MTO event

001: GPTM CH0O event




Others: Reserved – Should not be used to avoid unpredictable results

CMP Trigger Selection of ADC Conversion

0: CMP0

1: CMP1

BFTM or PWM Trigger Timer Selection of ADC Conversion

000: BFTM0

001: BFTM1

010: PWM0

011: PWM1

Others: Reserved – Should not be used to avoid unpredictable results

GPTM Trigger Timer Selection of ADC Conversion

000: Reserved

001: Reserved

010: GPTM

011: Reserved

Others: Reserved - Should not be used to avoid unpredictable results

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Bits

[11:8]

[0]

Field

ADEXTIS

ADSC

Descriptions

EXTI Trigger Source Selection of ADC Conversion

0x00: EXTI line 0

0x01: EXTI line 1

…

0x0F: EXTI line 15

Note that the EXTI line active edge to start an A/D conversion is determined in the

External Interrupt/Event Control Unit, EXTI.

ADC Conversion Software Trigger Bit

0: No operation

1: Start conversion immediately

This bit is set by software to start a conversion manually and then cleared by hardware automatically after conversion started.

ADC Watchdog Control Register – ADCWCR

This register provides the control bits and status of the ADC watchdog function.

Offset: 0x078


Type/Reset

Type/Reset

Type/Reset

Type/Reset

31

23

15

7

30

22

14

6

29

Reserved

21

Reserved

13

Reserved

5

Reserved

28

20

12

4

27 26 25

ADUCH

24

RO 0 RO 0 RO 0 RO 0

19 18 17 16

ADLCH

RO 0 RO 0 RO 0 RO 0

11 10 9

ADWCH

8

RW 0 RW 0 RW 0 RW 0

3 2 1

ADWALL ADWUE

0

ADWLE

RW 0 RW 0 RW 0

Bits

[27:24]

Field

ADUCH

Descriptions

Upper Threshold Channel Status

0000: ADC_IN0 converted data is higher than the upper threshold


...


Others: Reserved

If one of these status bits is set to 1 by the watchdog monitor function, the status field value should first be stored in the user-defined memory location in the corresponding ISR. Otherwise, the ADUCH field will be changed if another input channel converted data is higher than the upper threshold.

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[2]

[1]

[0]

Bits

[19:16]

[11:8]

Field

ADLCH

ADWCH

ADWALL

ADWUE

ADWLE

Descriptions

Lower Threshold Channel Status

0000: ADC_IN0 converted data is lower than the lower threshold


...


Others: Reserved

If one of these status bits is set to 1 by the watchdog monitor function, the status field value should first be stored in the user-defined memory location in the corresponding ISR. Otherwise, the ADLCH field will be changed if another input channel converted data is lower than the lower threshold.

ADC Watchdog Specific Channel Selection

0000: ADC_IN0 is monitored


...


Others: Reserved

ADC Watchdog Specific or All Channel Setting

0: Only the channel which specified by the ADWCH field is monitored

1: All channels are monitored

ADC Watchdog Upper Threshold Enable Bit

0: Disable upper threshold monitor function

1: Enable upper threshold monitor function

ADC Watchdog Lower Threshold Enable Bit

0: Disable lower threshold monitor function

1: Enable lower threshold monitor function

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ADC Watchdog Threshold Register – ADCTR

This register specifies the upper and lower threshold of the ADC watchdog function.

Offset: 0x07C


Type/Reset

31 30 29

Reserved

28 27 26 25

ADUT

24

RW 0 RW 0 RW 0 RW 0

23 22 21 20 19

ADUT

18 17 16


Type/Reset

15

7

14

6

13

Reserved

5

12

4

11

3

10

2

9

ADLT

1

8

RW 0 RW 0 RW 0 RW 0

0

ADLT


Bits

[27:16]

[11:0]

Field

ADUT

ADLT

Descriptions

ADC Watchdog Upper Threshold Value

Specify the upper threshold for the ADC watchdog monitor function.

ADC Watchdog Lower Threshold Value

Specify the lower threshold for the ADC watchdog monitor function.

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ADC Interrupt Enable Register – ADCIER

This register contains the ADC interrupt enable bits.

Offset: 0x080


31 30

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

29

21

13

5

Reserved

28

Reserved

20

Reserved

12

4

27

19

26

18

25 24

ADIEO

RW 0

17

ADIEU

16

ADIEL

RW 0 RW 0

9 8 11

Reserved

3

10

2

ADIEC

1

ADIEG

0

ADIES

RW 0 RW 0 RW 0

Bits

[24]

[17]

[16]

[2]

[1]

[0]

Field

ADIEO

ADIEU

ADIEL

ADIEC

ADIEG

ADIES

Descriptions

ADC Data Register Overwrite Interrupt enable

0: ADC data register overwrite interrupt is disabled

1: ADC data register overwrite interrupt is enabled

ADC Watchdog Upper Threshold Interrupt enable

0: ADC watchdog upper threshold interrupt is disabled

1: ADC watchdog upper threshold interrupt is enabled

ADC Watchdog Lower Threshold Interrupt enable

0: ADC watchdog lower threshold interrupt is disabled

1: ADC watchdog lower threshold interrupt is enabled

ADC Cycle EOC Interrupt enable

0: ADC cycle end of conversion interrupt is disabled

1: ADC cycle end of conversion interrupt is enabled

ADC Subgroup EOC Interrupt enable

0: ADC subgroup end of conversion interrupt is disabled

1: ADC subgroup end of conversion interrupt is enabled

ADC Single EOC Interrupt enable

0: ADC single end of conversion interrupt is disabled

1: ADC single end of conversion interrupt is enabled

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ADC Interrupt Raw Status Register – ADCIRAW

This register contains the ADC interrupt raw status bits.

Offset: 0x084


31 30

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

29

21

13

5

Reserved

28

Reserved

20

Reserved

12

4

27

19

26

18

25 24

ADIRAWO

RO 0

17 16

ADIRAWU ADIRAWL

RO 0 RO 0

9 8 11

Reserved

3

10

2 1 0

ADIRAWC ADIRAWG ADIRAWS

RO 0 RO 0 RO 0

Bits

[24]

[17]

[16]

[2]

[1]

[0]


ADIRAWO ADC Data Register Overwrite Interrupt Raw Status

0: ADC data register overwrite event does not occur

1: ADC data register overwrite event occurs

ADIRAWU ADC Watchdog Upper Threshold Interrupt Raw Status

0: ADC watchdog upper threshold event does not occur

1: ADC watchdog upper threshold event occurs

ADIRAWL ADC Watchdog Lower Threshold Interrupt Raw Status

0: ADC watchdog lower threshold event does not occurs

1: ADC watchdog lower threshold event occurs

ADIRAWC ADC Cycle EOC Interrupt Raw Status

0: ADC cycle end of conversion event does not occur

1: ADC cycle end of conversion event occurs

ADIRAWG ADC Subgroup EOC Interrupt Raw Status

0: ADC subgroup end of conversion event does not occur

1: ADC subgroup end of conversion event occurs

ADIRAWS ADC Single EOC Interrupt Raw Status

0: ADC single end of conversion event does not occur

1: ADC single end of conversion event occurs

Rev. 1.00 382 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

ADC Interrupt Status Register – ADCISR

This register contains the ADC interrupt status bits. The corresponding interrupt status will be set to 1 if the associated interrupt event occurs and the related enable bit is set to 1.

Offset: 0x088


31 30

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

29

21

13

5

Reserved

28

Reserved

20

Reserved

12

4

27

19

26

18

25 24

ADISRO

RO 0

17

ADISRU

16

ADISRL

RO 0 RO 0

9 8 11

Reserved

3

10

2 1 0

ADISRC ADISRG ADISRS

RO 0 RO 0 RO 0

Bits

[24]

[17]

[16]

[2]

[1]

[0]

Field

ADISRO

ADISRU

ADISRL

ADISRC

ADISRG

ADISRS

Descriptions

ADC Data Register Overwrite Interrupt Status

0: ADC data register overwrite interrupt does not occur or the data register overwrite interrupt is disabled.

1: ADC data register overwrite interrupt occurs as the data register overwrite interrupt is enabled.

ADC Watchdog Upper Threshold Interrupt Status

0: ADC watchdog upper threshold interrupt does not occur or the watchdog upper threshold interrupt is disabled.

1: ADC watchdog upper threshold interrupt occurs as the watchdog upper threshold interrupt is enabled.

ADC Watchdog Lower Threshold Interrupt Status

0: ADC watchdog lower threshold interrupt does not occur or the watchdog lower threshold interrupt is disabled.

1: ADC watchdog lower threshold interrupt occurs as the watchdog lower threshold interrupt is enabled.

ADC Cycle EOC Interrupt Status

0: ADC cycle end of conversion interrupt does not occur or the cycle end of conversion interrupt is disabled.

1: ADC cycle end of conversion interrupt occurs as the cycle end of conversion interrupt is enabled.

ADC Subgroup EOC Interrupt Status

0: ADC subgroup end of conversion interrupt does not occur or the subgroup end of conversion interrupt is disabled.

1: ADC subgroup end of conversion interrupt occurs as the subgroup end of conversion interrupt is enabled.

ADC Single EOC Interrupt Status

0: ADC single end of conversion interrupt does not occur or the single end of conversion interrupt is disabled.

1: ADC single end of conversion interrupt occurs as the single end of conversion interrupt is enabled.

Rev. 1.00 383 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

ADC Interrupt Clear Register – ADCICLR

This register provides the clear bits used to clear the interrupt raw and masked status of the ADC. These bits are set to 1 by software to clear the interrupt status and automatically cleared to 0 by hardware after being set to 1.

Offset: 0x08C


31 30

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

29

21

13

5

Reserved

28

Reserved

20

Reserved

12

4

27

19

26

18

25 24

ADICLRO

WO 0

17 16

ADICLRU ADICLRL

WO 0 WO 0

9 8 11

Reserved

3

10

2 1 0

ADICLRC ADICLRG ADICLRS

WO 0 WO 0 WO 0

Bits

[24]

[17]

[16]

[2]

[1]

[0]


ADICLRO ADC Data Register Overwrite Interrupt Status Clear Bit

0: No effect

1: Clear ADISRO and ADIRAWO bits

ADICLRU ADC Watchdog Upper Threshold Interrupt Status Clear Bit

0: No effect

1: Clear ADISRU and ADIRAWU bits

ADICLRL

ADICLRC

ADC Watchdog Lower Threshold Interrupt Status Clear Bit

0: No effect

1: Clear ADISRL and ADIRAWL bits

ADC Cycle EOC Interrupt Status Clear Bit

0: No effect

1: Clear ADISRC and ADIRAWC bits

ADICLRG ADC Subgroup EOC Interrupt Status Clear Bit

0: No effect

1: Clear ADISRG and ADIRAWG bits

ADICLRS ADC Single EOC Interrupt Status Clear Bit

0: No effect

1: Clear ADISRS and ADIRAWS bits

Rev. 1.00 384 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

ADC DMA Request Register – ADCDMAR

This register contains the ADC DMA request enable bits.

Offset: 0x090


31 30 29 28

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

21

13

5

Reserved

20

12

4

27

Reserved

19

Reserved

26

18

25

17

24

16

11

Reserved

3

10 9 8

2 1 0

ADDMAC ADDMAG ADDMAS

RW 0 RW 0 RW 0

Bits

[2]

[1]

[0]

Field

ADDMAC

ADDMAG

ADDMAS

Descriptions

ADC Cycle EOC DMA Request Enable Bit

0: ADC cycle end of conversion DMA request is disabled

1: ADC cycle end of conversion DMA request is enabled

ADC Subgroup EOC DMA Request Enable Bit

0: ADC subgroup end of conversion DMA request is disabled

1: ADC subgroup end of conversion DMA request is enabled

ADC Single EOC DMA Request Enable Bit

0: ADC single end of conversion DMA request is disabled

1: ADC single end of conversion DMA request is enabled

Rev. 1.00 385 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Voltage Reference Control Register – VREFCR

This register contains the internal voltage reference control bits.

Offset: 0x0A0


31

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

30

22

29

21

28

20

14 13 12

Reserved

6

Reserved

5 4

VREFSEL

RW 0 RW 0

27

Reserved

19

Reserved

11

3

26

18

10

2

Reserved

Bits

[8]

[5:4]

[0]


MVDDAEN Measurement V

0: Disable

DDA

/2 power Enable

1: Enable measurement V

DDA

/2 power

VREFSEL

VREFEN

Voltage Reference Output Selection

00: 1.215 V

01: 2.0 V

10: 2.5 V

11: 2.7 V

These bits select the Voltage Reference output level.

Voltage Reference Enable

0: Disable Voltage Reference

1: Enable Voltage Reference

25

17

24

16

9

1

8

MVDDAEN

RW 0

0

VREFEN

RW 0

Rev. 1.00 386 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Voltage Reference Value Register – VREFVALR

This register contains the internal voltage reference trim value.

Offset: 0x0A4

Reset value: 0x0000_00XX (Various depending on Flash Manufacture Privilege Information Block)

31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

Type/Reset

Type/Reset

15 14 13 12 11

Reserved

10 9 8

7

Reserved

6 5 4 3

VREFVAL

2 1 0

RO X RO X RO X RO X RO X RO X RO X

Bits

[6:0]

Field

VREFVAL

Descriptions

Voltage Reference Calibration Value

During the manufacturing process, the calibration data of the internal voltage reference is stored in the Flash Manufacture Privilege Information Block and downloaded to this filed when the system is powered on.

Rev. 1.00 387 of 637 December 28, 2020

32-Bit Arm ®

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Cortex ® -M0+ MCU

20

Comparator (CMP)

Introduction

Two general purpose comparators (CMP) are implemented within the device. They can be configured either as standalone comparators or combined with the different kinds of peripheral IP.

Each comparator is capable of asserting interrupts to the NVIC or waking up the CPU from the

Sleep, Deep-Sleep1 or Deep-Sleep2 mode through the EXTI wakeup event management unit.

Comparator Analog IP

Programmable

Hysteresis

CMPEN

CP

CN

Reserved

Reserved

V

DDA

0

V

REF 1

CVRSS

V

SSA

CVREN

8-Bit

CVR

CVRVAL[7:0]

CMPINSEL[1:0]

Programmable

Response Time

V

CVR

CVROE

V

DDA

Domain

Figure 103. Comparator Block Diagram

0

1

CMPPOL

V

CORE

Domain

CMPOUT

Sync

0

CMPSTS

1

PCLK

GPIO

AFIO

SYNCSEL

Control &

Interrupt

Generator

CMP Status

& Interrupt

Reguest

ADC

GPTM

To EXTI

Wakeup

Event

Management

COUT

Features

▆

Rail-to-rail comparator

▆

▆

▆

▆

▆

▆

Configurable negative inputs for flexible voltage selection

● External CN pin

● Internal 8-bit CVR output

Programmable hysteresis

Programmable response speed and power consumption

Comparator output can be routed to I/O pin, to multiple timers or to ADC trigger inputs

8-bit CVR can be configured to dedicate I/O for voltage reference

Comparator has interrupt generation capability with wakeup function from the Sleep, Deep-

Sleep1 or Deep-Sleep2 mode through the EXTI controller

Rev. 1.00 388 of 637 December 28, 2020

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Cortex ® -M0+ MCU


Comparator Inputs and Output

The I/O pins used as comparator input or output must be configured in the AFIO controller registers. The detailed comparator input and output information will be referred in pin assignment table in the datasheet. The output can also be internally connected to a variety of timers or ADC for trigger purpose. The comparator output can simultaneously be used for both internal and external functions.

Comparator Voltage Reference

The comparator voltage reference is a 256-tap resistor ladder network that provides a selectable reference voltage. A block diagram of the comparator voltage reference is shown in Figure 104. It also has a power-down function to conserve power when the reference is not used. The comparator voltage reference provides 256 distinct levels. The equation used to calculate the value of the reference voltage is as follows:

V

CVR

= CVRVAL × (V

RP

- V

SSA

) / 255

The supply voltage V

RP

can come from either the V

DDA

or the internal voltage reference V

REF by configuring the CVRSS bit in the Comparator Control Register CMPCRn. The CVR output

V

CVR

is used to provide a reference voltage for the analog comparator. It can be internally used or configured to connect to the CN pin by setting the CVROE bit in the Comparator Control Register

CMPCRn . The settling time of the comparator voltage reference must be considered when the V

CVR output voltage is changed.

V

DDA

V

REF

CVRSS = 0

CVRSS = 1

V

RP

CVRVAL[7:0]

CVREN

R

R

R

R V

CVR

R

R

R

Figure 104. Comparator Voltage Reference Block Diagram

Rev. 1.00 389 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Interrupts and Wakeup

The comparator can generate an interrupt when its output waveform generates a rising or falling edge and its corresponding interrupt enable control bit is also set.

For example, when a comparator output rising edge occurs, the comparator rising edge flag bit

CMPRF in the Comparator Transition Flag Register CMPTFRn will be set. If the comparator output rising edge interrupt enable control bit CMPRIEN in the Comparator Interrupt Enable

Register CMPIERn is enabled, an interrupt will then be generated and sent to the NVIC unit.

Writing “1” into the comparator rising edge flag bit CMPRF in the Comparator Transition Flag

Register CMPTFRn will clear the CMPRF bit. The comparator output falling edge interrupt also has the same corresponding interrupt setting. A block diagram of interrupt signals for comparators is shown in Figure 105.

CMPRF

CMPRIEN

CMP0

CMPFF

CMPFIEN

NVIC CMP Interrupt

CMPRF

CMPRIEN

CMP1

CMPFF

CMPFIEN

Figure 105. Comparator Interrupt Signals

The comparator outputs are also internally connected to the EXTI Wakeup Event Management unit. The comparator output rising transition is used to wake up the MCU from the Sleep, Deep-

Sleep1 or Deep-Sleep2 mode when the comparator wakeup enable bit CMPWPEN is set in the

Comparator Control Register CMPCR n. A block diagram of wakeup signal for each comparator is shown in Figure 106.

CMP0

CMPWPEN

CMPOUT

EXTI

CMP_WAKEUP

CMP1

CMPWPEN

CMPOUT

Figure 106. Comparator Wakeup Signal

Rev. 1.00 390 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Power Mode and Hysteresis

The comparator response time can be programmed to meet the trade-off between the power consumption and application speed requirements. The bit CMPSM in the CMPCRn register can be programmed as “0” to make the comparator operate in the low speed mode with low power consumption.

The comparator also has four hysteresis levels to avoid spurious output transitions in case of noisy signals. The bits CMPHM[1:0] in the CMPCRn register can be configured to obtain different hysteresis levels for the comparator.

Comparator Write-Protected Mechanism

As the comparator can be used for safety purposes, it is necessary to ensure that the comparator configurations will not be altered due to spurious register access or program counter corruption.

For this purpose, the write-protected function is provided by writing a specific value into the

PROTECT filed in the Comparator Control Register CMPCRn. The write-protected function is enabled by default. Before configuring the bits [15:0] in the Comparator Control Register CMPCRn, the pattern, 0x9C3A, must first be written into the register protection bits [31:16] in the CMPCRn register. Then the write-protected function will be disabled and the bits [15:0] can be configured by application program. For the same reason, the comparator input and output can also be locked using the corresponding configuration lock bit in the Port n Lock Register PnLOCKR (n = A ~ E) in the

GPIO unit.

Register Map

The following table shows the CMP registers and reset values.

Table 57. CMP Register Map

Register

CMPCR0

CVRVALR0

Offset

0x000

0x004

Description

Comparator Control Register 0

Comparator Voltage Reference Value Register 0

CMPIER0

CMPTFR0

CMPCR1

CVRVALR1

CMPIER1

CMPTFR1

0x008

0x00C

0x100

0x104

0x108

0x10C

Comparator Interrupt Enable Register 0

Comparator Transition Flag Register 0

Comparator Control Register 1

Comparator Voltage Reference Value Register 1

Comparator Interrupt Enable Register 1

Comparator Transition Flag Register 1

Reset Value

0x0001_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0001_0000

0x0000_0000

0x0000_0000

0x0000_0000

Rev. 1.00 391 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU


Comparator Control Register n – CMPCRn, n = 0 or 1

This register contains the comparator function and voltage reference control bits.

Offset: 0x000 (n = 0), 0x100 (n = 1)


31 30 29 28 27

PROTECT

26 25 24


23 22 21 20 19

PROTECT

18 17 16


15 14

CMPSTS CMPWPEN

13 12

CMPOSEL

11 10

CVRSS

9

CVROE

8

CVREN

Type/Reset RO 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0

7 6 5 4 3 2 1 0

SYNCSEL CMPPOL CMPINSEL CMPHM CMPSM CMPEN


Bits

[31:16]

[15]

[14]


PROTECT Register Protection

For write operation:

0x9C3A: Disable the CMPCRn register write protection

Others values: Enable the CMPCRn register write protection

For read operation:

0x0000: CMPCRn register write protection is disabled

0x0001: CMPCRn register write protection is enabled

These bits are used to enable or disable the write protection of the filed [14:0] in the CMPCRn register. Enabling the write protection will make the filed [14:0] in the

CMPCRn register become read-only to prevent any unexpected write operation.

The value read from this field indicates if the write protection is enabled or not.

CMPSTS Comparator Output Status

0: Output is low

1: Output is high

This read-only bit is a copy of the comparator output state after the polarity selection and synchronization.

CMPWPEN Comparator Wakeup Enable

0: Disable comparator wakeup function

1: Enable comparator wakeup function

This bit is used to enable the MCU wakeup function from the Sleep, Deep-Sleep1 or Deep-Sleep2 mode when the comparator output after the polarity selection occurring the rising transition event.

Rev. 1.00 392 of 637 December 28, 2020

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HT32F5828

Cortex ® -M0+ MCU

[1]

[0]

[10]

[9]

[8]

Bits

[13:11]

[7]

[6]

[5:4]

[3:2]


CMPOSEL Comparator 0 Output Selection

000: No selection

001: GPTM capture channel 3

100: ADC trigger input

Others: Reserved

Comparator 1 Output Selection

000: No selection

001: GPTM capture channel 3

100: ADC trigger input

Others: Reserved

These bits are used to select the destination for the comparator output after the polarity selection and synchronization.

CVRSS Comparator Voltage Reference Source Selection

0: 8-bit CVR supply voltage comes from V

DDA

1: 8-bit CVR supply voltage comes from internal voltage reference V

REF

CVROE

CVREN

SYNCSEL

Comparator Voltage Reference Output Enable

0: Disable 8-bit CVR output to CN pin

1: Enable 8-bit CVR output to CN pin

Comparator Voltage Reference Enable

0: Disable 8-bit CVR

1: Enable 8-bit CVR

Setting this bit will enable the CVR to output a configured reference voltage.

Synchronization Selection

0: Asynchronous signal of comparator output is selected

1: Synchronous signal of comparator output is selected

The synchronous comparator output should be selected before being passed to the

AFIO unit.

CMPPOL

CMPINSEL Comparator Inverted Input Selection

00: External CN pin

01: Internal 8-bit CVR output

1x: Reserved

These bits are used to select the comparator inverted input source.

CMPHM

Comparator Output Polarity Selection

0: Comparator output is not inverted

1: Comparator output is inverted

Comparator Hysteresis Mode Selection

00: No hysteresis

01: Low hysteresis mode

10: Middle hysteresis mode

11: High hysteresis mode

CMPSM

CMPEN

Comparator Response Speed Mode Selection

0: Low speed mode

1: High speed mode

Comparator Enable

0: Disable Comparator

1: Enable Comparator

Rev. 1.00 393 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Comparator Voltage Reference Value Register n – CVRVALRn, n = 0 or 1

The register is used to set the comparator voltage reference level.

Offset: 0x004 (n = 0), 0x104 (n = 1)


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

Reserved

10 9 8

Type/Reset

7 6 5 4 3

CVRVAL

2 1 0


Bits

[7:0]

Field

CVRVAL

Descriptions

Comparator Voltage Reference Value

There are 256 levels of the comparator voltage reference, which is set using the

CVRVAL bits. The relationship between the CVRVAL field value and the CVR output,

V

V

CVR

CVR

, is given by the following equation:

= CVRVAL × (V

RP

- V

SSA

) / 255, where V

RP

can come from the V

DDA

or V

REF

.

Rev. 1.00 394 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Comparator Interrupt Enable Register n – CMPIERn, n = 0 or 1

The register is used to enable the comparator n interrupt when the comparator output transition event occurs.

Offset: 0x008 (n = 0), 0x108 (n = 1)


31 30 29 26 25 24

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

21

13

5

28

20

27

Reserved

19

Reserved

12

4

Reserved

11

Reserved

3

18

10

2

17

9

16

8

1 0

CMPRIEN CMPFIEN

RW 0 RW 0

Bits

[1]

[0]


CMPRIEN Comparator Output Rising Edge Interrupt Enable

0: Disable comparator output rising edge interrupt

1: Enable comparator output rising edge interrupt

CMPFIEN Comparator Output Falling Edge Interrupt Enable

0: Disable comparator output falling edge interrupt

1: Enable comparator output falling edge interrupt

Rev. 1.00 395 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Comparator Transition Flag Register n – CMPTFRn, n = 0 or 1

This register contains the comparator n output transition detection enable bits and relevant flags.

Offset: 0x00C (n = 0), 0x10C (n = 1)


31 30 29 26 25

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

21

13

5

28

20

12

Reserved

4

Reserved

27

Reserved

19

Reserved

11

3

18

10

2

17

24

16

9 8

CMPRDEN CMPFDEN

RW 0 RW 0

1 0

CMPRF CMPFF

WC 0 WC 0

Bits

[9]

[8]

[1]

[0]


CMPRDEN Comparator Output Rising Edge Detection Enable

0: Disable comparator output rising edge detection

1: Enable comparator output rising edge detection

Note that the signal to be detected is a copy of the comparator output state after the polarity selection and synchronization by the PCLK clock.

CMPFDEN Comparator Output Falling Edge Detection Enable

0: Disable comparator output falling edge detection

1: Enable comparator output falling edge detection

Note that the signal to be detected is a copy of the comparator output state after the polarity selection and synchronization by the PCLK clock.

CMPRF Comparator Output Rising Edge Flag

0: No comparator output rising edge occurs

1: Comparator output rising edge occurs

This flag is available when the comparator output rising edge detection is enabled.

This bit is set to 1 by hardware and cleared to 0 by writing a “1” into it.

CMPFF Comparator Output Falling Edge Flag

0: No Comparator output falling edge occurs

1: Comparator output falling edge occurs

This flag is available when the comparator output falling edge detection is enabled.

This bit is set to 1 by hardware and cleared to 0 by writing a “1” into it.

Rev. 1.00 396 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

21

Digital to Analog Converter (DAC)

Introduction

A 12-bit Digital to Analog Converter (DAC) module is integrated in the device. The DAC module has two output channels with which each has its own converter and output buffer. The two channel data conversions can be stand-alone implementation in asynchronous mode or be simultaneous implementation in synchronous mode.

DACxDHR

8/12-bit

DACxCR

Control logic

VDDA

VSSA

Internal

Voltage

Reference

(V

REF

)

VREFSEL[1:0]

12-bit

DACxDOR

12-bit

DACEN

V

DACREF

Digital to Analog

Converterx DON

DBON

DACx_OUT x: 0~1

Figure 107. DAC Channel Block Diagram

Features

▆

▆

▆

▆

▆

Two DAC channels with respective output buffer independent or simultaneous conversion

8-bit / 12-bit right alignment data format

Maximum 500 ksps conversion rate

Voltage Reference from Internal Voltage Reference V

REF

or V

DDA

Rev. 1.00 397 of 637 December 28, 2020

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HT32F5828

Cortex ® -M0+ MCU

Function Descriptions

DAC Channel Enable

Each DAC channel can be powered on by setting the corresponding DACEN bit in the DACxCR register. It should be noted that the DACEN bit only enables the analog D/A converter. The digital

DAC controller is enabled by the DACCEN bit in the APBCCR1 register located in the CKCU unit.

DAC Operation Mode

The two DAC channels can be operated in synchronous mode which converts two channel data simultaneously by setting the MODE bit in the DACCFGR register or in asynchronous mode which converts two channel data independently by clearing the MODE bit.

Whenever in the synchronous mode or asynchronous mode, the DAC clock source is the same for the DAC CH0 and CH1 channel.

DAC Asynchronous Conversion

In the asynchronous mode, the data conversion of each DAC channel is performed by loading data into the corresponding DACxDHR register. And the data will automatically be transferred into the

DACxDOR register at the next DAC clock cycle.

t

When the DACxDOR register is loaded, the analog output voltage becomes available after a time

SETTLE

that depends on the power supply and the analog output load.

PCLK_DAC

DACxDHR

0x945

DACxDOR

Figure 108. DAC Data Transfer Timing Diagram

0x945 t

SETTLE

Output voltage is available on the DACx_OUT pin

The data format for the DACxDHR register is right alignment. In 8-bit data resolution setting, the hardware will pad 4 bits of zero into the LSB automatically when the DACxDOR register is loaded.

DACxDHR

31 15 11 0

DACxDATA

31

DACxDOR

15

Figure 109. 12-bit Data Transfer in Asynchronous Mode

Rev. 1.00 398 of 637

11

DACxDATA

0

December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

31

DACxDHR

15 7

DACxDATA

0

DACxDOR

31 15 11

DACxDATA

4

0000

0

Figure 110. 8-bit Data Transfer in Asynchronous Mode

DAC Synchronous Conversion

In the synchronous mode, the data conversion of two DAC channel are performed the MCU writes a DAC output by simultaneously trigger data into the DAC0DHR register. And the data will automatically be transferred into the corresponding DAC0DOR and DAC1DOR register at the next

DAC clock cycle.

The DAC data resolution setting in this mode is determined by the DACRES bit in the DAC0CR register.

31

DAC0DHR

27 16 11 0

DAC1DATA DAC0DATA

31

DAC0DOR

31

DAC1DOR

Figure 111. 12-bit Data Transfer in Synchronous Mode

15

11

DAC0DATA

0

15 11 0

DAC1DATA

Rev. 1.00 399 of 637 December 28, 2020

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Cortex ® -M0+ MCU

31

DAC0DHR

15

DAC1DATA

7

DAC0DATA

0

31

DAC0DOR

15 11

DAC0DATA

4

0000

0

31

DAC1DOR

15 11

DAC1DATA

4

0000

0

Figure 112. 8-bit Data Transfer in Synchronous Mode

DAC Output Voltage

The 12-bit digital data is converted to analog voltage on a linear conversion between 0 and V

The DAC voltage reference V analog power V

DDA

.

DACREF

can be selected from the Internal Voltage Reference V

DACREF

.

REF

or the

The output voltage on each DAC channel is determined by the following equation:

DACx_OUT = DACxDOR × (V

DACREF

/ 4095)

DAC Output Buffer

Two output buffers are integrated that can be used to drive external loads directly. Each DAC channel output buffer can be enabled or disabled by configuring the corresponding DBON bit in the DACxCR register. It should be noted that both DBON bit and DON bit cannot be set at the same time, otherwise it will lead to unpredictable results.

Register Map

The following table shows the DAC register and reset value.

Table 58. DAC Register Map

Register

DACCFGR

Offset

0x000

Description

DAC Configuration Register

DAC0CR

DAC0DHR

DAC0DOR

DAC1CR

DAC1DHR

DAC1DOR

0x010

0x01C

0x020

0x030

0x03C

0x040

DAC Channel 0 Control Register

DAC Channel 0 Data Holding Register

DAC Channel 0 Data Output Register

DAC Channel 1 Control Register

DAC Channel 1 Data Holding Register

DAC Channel 1 Data Output Register

Reset Value

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

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Cortex ® -M0+ MCU


DAC Configuration Register – DACCFGR

This register specifies the DAC global configuration.

Offset: 0x000


31 30 29

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

21

13

5

28

20

27

Reserved

19

Reserved

12

4

Reserved

11

Reserved

3

Type/Reset

Bits

[0]

Field

MODE

Descriptions

Conversion Mode Selection

0: Asynchronous mode

1: Synchronous mode

26

18

10

2

25

17

24

16

9 8

1 0

MODE

RW 0

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Cortex ® -M0+ MCU

DAC Channel 0 Control Register – DAC0CR

This register specifies the DAC channel 0 configurations and enable bits.

Offset: 0x010


29 31 30

Type/Reset

23 22

Type/Reset

15 14

VREFSEL


7 6

DBON DON


21

13

5

28

20

12

4

Reserved

27

Reserved

19

Reserved

11

3

26

18

25

17

24

16

10

Reserved

9 8

2 1 0

DACRES Reserved DACEN

RW 0 RW 0

Bits

[15:14]

[7]

[6]

[2]

[0]


VREFSEL DAC Channel Voltage Reference Source Selection

00: V

01: V

DDA

REF

Others: Reserved

DBON

DON

DACRES

DACEN

DAC Channel Output Buffer Enable

0: DAC channel output buffer is disabled

1: DAC channel output buffer is enabled

DAC Channel Directly Output Enable

0: DAC channel directly output is disabled

1: DAC channel directly output is enabled

DAC Channel Resolution Selection

0: 12-bit resolution

1: 8-bit resolution

If the DAC is operated in the synchronous mode, the DAC resolution is determined by the DACRES bit in the DAC0CR register, in such case the same bit in the

DAC1CR will be ignored.

DAC Channel Enable

0: DAC channel is disabled

1: DAC channel is enabled

Users should select only one DAC output path from DAC output, namely with buffer or directly output by configuring the DBON or DON bit respectively. It is forbidden to set both DBON and DON bits high at the same time, otherwise it will lead to unpredictable results.

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HT32F5828

Cortex ® -M0+ MCU

DAC Channel 0 Data Holding Register – DAC0DHR

This register contains the right alignment data for DAC channel 0 and DAC channel 1.

Offset: 0x01C


Type/Reset

31 30 29

Reserved

28 27 26 25

DAC0DATA

24

RW 0 RW 0 RW 0 RW 0

23 22 21 20

DAC0DATA

19 18 17 16


15 14 13 12

DAC0DATA

11 10 9 8


7 6 5 4 3 2 1 0

DAC0DATA


Bits

[27:0]


DAC0DATA DAC Channel 0 Holding Data

In the asynchronous mode:

- For 8-bit resolution: DAC channel 0 data should be loaded into the DAC0DHR

[7:0] bits


[11:0] bits

In the synchronous mode:


[7:0] bits and DAC channel 1 data should be loaded into the DAC0DHR [15:8] bits


[11:0] bits and DAC channel 1 data should be loaded into the DAC0DHR [27:16] bits

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Cortex ® -M0+ MCU

DAC Channel 0 Data Output Register – DAC0DOR

This register contains the data output for DAC channel 0.

Offset: 0x020


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

Type/Reset

15

7

14

6

13

Reserved

5

12 11 10

DAC0DOUT

9 8

RO 0 RO 0 RO 0 RO 0

4

DAC0DOUT

3 2 1 0


Bits

[11:0]


DAC0DOUT DAC Channel 0 Data Output

These bits contain data output for DAC channel 0.

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Cortex ® -M0+ MCU

DAC Channel 1 Control Register – DAC1CR

This register specifies the DAC channel 1 configurations and enable bits.

Offset: 0x030


29 31 30

Type/Reset

23 22

Type/Reset

15 14

VREFSEL


7 6

DBON DON


21

13

5

28

20

12

4

Reserved

27

Reserved

19

Reserved

11

3

26

18

25

17

24

16

10

Reserved

9 8

2 1 0

DACRES Reserved DACEN

RW 0 RW 0

Bits

[15:14]

[7]

[6]

[2]

[0]


VREFSEL DAC Channel Voltage Reference Source Selection

00: V

01: V

DDA

REF

Others: Reserved

DBON

DON

DACRES

DACEN

DAC Channel Output Buffer Enable

0: DAC channel output buffer is disabled

1: DAC channel output buffer is enabled

DAC Channel Directly Output Enable

0: DAC channel directly output is disabled

1: DAC channel directly output is enabled

DAC Channel Resolution Selection

0: 12-bit resolution

1: 8-bit resolution

If the DAC is operated in the synchronous mode, the DAC resolution is determined by the DACRES bit in the DAC0CR register, in such case the same bit in the

DAC1CR will be ignored.

DAC Channel Enable

0: DAC channel is disabled

1: DAC channel is enabled

Users should select only one DAC output path from DAC output, namely with buffer or directly output by configuring the DBON or DON bit respectively. It is forbidden to set both DBON and DON bits high at the same time, otherwise it will lead to unpredictable results.

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HT32F5828

Cortex ® -M0+ MCU

DAC Channel 1 Data Holding Register – DAC1DHR

This register contains the right alignment data for DAC channel 1.

Offset: 0x03C


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

Type/Reset

15

7

14

6

13

Reserved

5

12 11 10

DAC1DATA

9 8

RW 0 RW 0 RW 0 RW 0

4

DAC1DATA

3 2 1 0


Bits

[11:0]


DAC1DATA DAC Channel 1 Holding Data

In the asynchronous mode:


[7:0] bits


[11:0] bits

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HT32F5828

Cortex ® -M0+ MCU

DAC Channel 1 Data Output Register – DAC1DOR

This register contains the data output for DAC channel 1.

Offset: 0x040


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

Type/Reset

15

7

14

6

13

Reserved

5

12 11 10

DAC1DOUT

9 8

RO 0 RO 0 RO 0 RO 0

4

DAC1DOUT

3 2 1 0


Bits

[11:0]


DAC1DOUT DAC Channel 1 Data Output

These bits contain data output for DAC channel 1.

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22

General-Purpose Timer (GPTM)

Introduction

The General-Purpose Timer consists of one 16-bit up/down-counter, four 16-bit Capture/

Compare Registers (CCRs), one 16-bit Counter-Reload Register (CRR) and several control/status registers. It can be used for a variety of purposes including general timer, input signal pulse width measurement or output waveform generation such as single pulse generation or PWM output. The

GPTM supports an encoder interface using a quadrature decoder with two inputs.

ITI0

ITI1

ITI2

Edge

Detector

UEVG

TI0BED

TI0S0ED

TI1S1ED

TI0S1ED

TI1S0ED

TI0S0

TI1S1 f

CLKIN

TRCED

Quadrature

Decoder

STIED

CLKPULSE

Clock

Controller

UEVG

TEV

TME

UEV

CHxOREF

(x = 0 ~ 3)

CEVx

MDCFR

Register

STI

Up/Dn

Control

Slave

Controller

Master

Controller

MTO

To other Timers,

ADC and so on

TEV : Trigger Event

CEVx : Channel x Capture Event

MEVx : Channel x Compare Match Event

UEV : Update Event

GT_CH0

GT_CH1

GT_CH2

XOR

TI0

TI1

Input Filter

& Polarity Selection

& Edge Detection

TI0S0ED

TI0S1ED

Input Filter


& Edge Detection

TI1S0ED

TI1S1ED

TI2 Input Filter


& Edge Detection

TI2S2ED

TI2S3ED

GT_CH3

TI3

Input Filter


& Edge Detection

TI3S2ED

TI3S3ED

TRCED

Figure 113. GPTM Block Diagram

CK_PSC PSC

PRESCALER

CK_CNT

Restart

Pause

Trigger

Up/Dn

Reload Register

TM_CNT

(CRR)

UEV

CH0

PRESCALER

CH1

PRESCALER

CH2

PRESCALER

CH3

PRESCALER

CEV0

CEV1

CEV2

CEV3

CH0 Capture/Compare

Register (CH0CCR)

MEV0

CH0OREF Output

Control



MEV1

CH1OREF Output

Control



MEV2

CH2OREF Output

Control



MEV3

CH3OREF Output

Control

GT_CH0O

GT_CH1O

GT_CH2O

GT_CH3O

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HT32F5828

Cortex ® -M0+ MCU

Features

▆

▆

▆

▆

▆

▆

▆

16-bit up/down auto-reload counter

16-bit programmable prescaler that allows division of the prescaler clock source by any factor between 1 and 65536 to generate the counter clock frequency

Up to 4 independent channels for:

● Input Capture function

● Compare Match Output

● Generation of PWM waveform – Edge and Center-aligned Mode

● Single Pulse Mode Output

Encoder interface controller with two inputs using quadrature decoder

Synchronization circuit to control the timer with external signals and to interconnect several timers together

Interrupt/PDMA generation with the following events:

● Update event

●

● Input capture event

●

Trigger event

Output compare match event

GPTM Master/Slave mode controller


Counter Mode

Up-Counting

In this mode the counter counts continuously from 0 to the counter-reload value, which is defined in the CRR register, in a count-up direction. Once the counter reaches the counter-reload value, the Timer Module generates an overflow event and the counter restarts to count once again from

0. This action will continue repeatedly. The counting direction bit DIR in the CNTCFR register should be set to 0 for the up-counting mode.

When the update event is generated by setting the UEVG bit in the EVGR register to 1, the counter value will also be initialized to 0.

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Cortex ® -M0+ MCU

CK_PSC

CNT_EN

CK_CNT

CNTR

CRR

CRR Shadow

Register

PSCR

PSCR Shadow

Register

PSC_CNT

Counter Overflow

Update Event Flag

F5

F2

0

F5

0

0

F3

Write a new value

Figure 114. Up-counting Example

F4 F5

0

0

Update the new value

1

36

0

1

1

1

36

1

0

2

1

Software clearing

0

3

1

Down-Counting

In this mode the counter counts continuously from the counter-reload value, which is defined in the CRR register, to 0 in a count-down direction. Once the counter reaches 0, the Timer module generates an underflow event and the counter restarts to count once again from the counter-reload value. This action will continue repeatedly. The counting direction bit DIR in the CNTCFR register should be set to 1 for the down-counting mode.

When the update event is set by the UEVG bit in the EVGR register, the counter value will also be initialized to the counter-reload value.

CK_PSC

CNT_EN

CK_CNT

CNTR

CRR

CRR Shadow

Register

PSCR

PSCR Shadow

Register

PSC_CNT

Counter Underflow

Update Event Flag

F5

3

0

F5

0

0

2

Write a new value

Figure 115. Down-counting Example

1 0

0

36

Update a new value

1

36

0

35

1

1

36

1

0

34

Software clearing

1

33

0 1

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Cortex ® -M0+ MCU

Center-Aligned Counting

In the center-aligned counting mode, the counter counts up from 0 to the counter-reload value and then counts down to 0 alternatively. The Timer module generates an overflow event when the counter counts to the counter-reload value in the up-counting mode and generates an underflow event when the counter counts to 0 in the down-counting mode. The counting direction bit DIR in the CNTCFR register is read-only and indicates the counting direction when in the center-aligned mode. The counting direction is updated by hardware automatically.

Setting the UEVG bit in the EVGR register will initialize the counter value to 0 irrespective of whether the counter is counting up or down in the center-aligned counting mode.

The update event interrupt flag bit in the INTSR register will be set to 1, when an overflow or underflow event occurs.

CK_PSC

CNT_EN

CK_CNT

CNTR

CRR

CRR Shadow

Register

Counter Overflow

Counter Underflow

Update Event Flag

F2

F5

F5

F3 F4 4

Write a new value

Figure 116. Center-aligned Counting Example

3 2

Software clearing

4

1

4

0 1 2

Software clearing

3

Clock Controller

The following describes the Timer Module clock controller which determines the clock source of the internal prescaler counter.

▆

Internal APB clock f

CLKIN

:

The default internal clock source is the APB clock f

CLKIN

used to drive the counter prescaler when the slave mode is disabled. When the slave mode selection bits SMSEL in the MDCFR register are set to 0x4, 0x5 or 0x6, the internal APB clock f

CLKIN

is the counter prescaler driving clock source. If the slave mode controller is enabled by setting SMSEL field in the MDCFR register to an available value including 0x1, 0x2, 0x3 and 0x7, the prescaler is clocked by other clock sources selected by the TRSEL field in the TRCFR register and described as follows.

▆

Quadrature Decoder:

To select Quadrature Decoder mode the SMSEL field should be set to 0x1, 0x2 or 0x3 in the

MDCFR register. The Quadrature Decoder function uses two input states of the GT_CH0 and

GT_CH1 pins to generate the clock pulse to drive the counter prescaler. The counting direction bit DIR is modified by hardware automatically at each transition on the input source signal. The input source signal can be derived from the GT_CH0 pin only, the GT_CH1 pin only or both

GT_CH0 and GT_CH1 pins.

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Cortex ® -M0+ MCU

CLKPULSE

(Quadrature Decoder) f

CLKIN

(Internal APB clock)

STIED

(Trigger events)

▆

STIED:

The counter prescaler can count during each rising edge of the STI signal. This mode can be selected by setting the SMSEL field to 0x7 in the MDCFR register. Here the counter will act as an event counter. The input event, known as STI here, can be selected by setting the TRSEL field to an available value except the value of 0x0. When the STI signal is selected as the clock source, the internal edge detection circuitry will generate a clock pulse during each STI signal rising edge to drive the counter prescaler. It is important to note that if the TRSEL field is set to

0x0 to select the software UEVG bit as the trigger source, then when the SMSEL field is set to

0x7, the counter will be updated instead of counting.

PSCR CRR

CK_PSC

CLK

PSC Prescaler

Reset

CK_CNT

CLK

CNTR

Reset

Update Event

TM_CNT

TRSEL

SMSEL

Start/Stop

Figure 117. GPTM Clock Source Selection

Overflow /

Underflow UEVG bit

Slave Restart mode trigger

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Trigger Controller

The trigger controller is used to select the trigger source and setup the trigger level or trigger edge condition. For the internal trigger input, it can be selected by the Trigger Selection bits TRSEL in the TRCFR register. For all the trigger sources except the UEVG bit software trigger, the internal edge detection circuitry will generate a clock pulse at each trigger signal rising edge to stimulate some GPTM functions which are triggered by a trigger signal rising edge.

Trigger Controller Block = Edge Trigger Mux + Level Trigger Mux

Internal Trigger Input

ITI0

ITI1

ITI2

Edge

Detection

ITI0ED

ITI1ED f

CLKIN

ITI2ED

Edge Trigger Source = Internal (ITIx) + Channel input (TIn)

Edge Trigger Mux

0

TI0S0ED

TI1S1ED

Reserved

Reserved

TRSEL[2:0]

TI0BED

ITI0ED

ITI1ED

ITI2ED

Reserved

000

001

010

011 others

STIED_S1

000

001

010

011 others

STIED_S0

0

1

TRSEL[3]

STIED

TRCED

Level Trigger Source = Internal (ITIx) + Channel input (TIn) + Software UEVG bit

S/W Set

UEVG Bit

TI0S0

TI1S1

Level Trigger Mux

Reserved

Reserved

TRSEL[2:0]

0

ITI0

ITI1

ITI2

Reserved

000

001

010

011 others

STI_S1

000

001

010

011 others

STI_S0

0

1

TRSEL[3]

STI

Figure 118. Trigger Controller Block

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Slave Controller

The GPTM can be synchronized with an external trigger in several modes including the Restart mode, the Pause mode and the Trigger mode which can be selected by the SMSEL field in the

MDCFR register. The trigger input of these modes comes from the STI signal which is selected by the TRSEL field in the TRCFR register. The operation modes in the Slave Controller are described in the accompanying sections.

Trigger Controller

STI

Slave

Controller

Trigger Event

Reset/Stop/Start Counter

SMSEL Restart/Pause/Trigger Mode

Figure 119. Slave Controller Diagram

Restart Mode

The counter and its prescaler can be reinitialized in response to a rising edge of the STI signal.

When an STI rising edge occurs, the update event software generation bit named UEVG will automatically be asserted by hardware and the trigger event flag will also be set. Then the counter and prescaler will be reinitialized. Although the UEVG bit is set to 1 by hardware, the update event does not really occur. It depends upon whether the update event disable control bit UEVDIS is set to 1 or not. If the UEVDIS is set to 1 to disable the update event to occur, there will no update event be generated, however the counter and prescaler are still reinitialized when the STI rising edge occurs. If the UEVDIS bit in the CNTCFR register is cleared to enable the update event to occur, an update event will be generated together with the STI rising edge, then all the preloaded registers will be updated.

Timer Counter Reload Register CRR = 32

STI source signal

(polarity=0)

STI source signal

(polarity=1)

STI

CK_CNT

UEVG bit

(reset counter)

CNTR

(Up-counting)

CNTR

(Down-counting)

TEVIF

27

27

28

26

29

25

Figure 120. GPTM in Restart Mode

Sync.

30

24

31

23

Trigger Event

0

32

1

31

2

30

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Pause Mode

In the Pause Mode, the selected STI input signal level is used to control the counter start/stop operation. The counter starts to count when the selected STI signal is at a high level and stops counting when the STI signal is changed to a low level, here the counter will maintain its present value and will not be reset. Since the Pause function depends upon the STI level to control the counter stop/start operation, the selected STI trigger signal can not be derived from the TI0BED signal.

STI source signal

(polarity=0)

STI source signal

(polarity=1)

STI

CK_ CNT

CNT_ EN

CNTR

TEVIF

Sync

27 28 29

Sync

30 31

Software clearing

Figure 121. GPTM in Pause Mode

Trigger Mode

After the counter is disabled to count, the counter can resume counting when an STI rising edge signal occurs. When an STI rising edge occurs, the counter will start to count from the current value in the counter. Note that if the STI signal is selected to be derived from the UEVG bit software trigger, the counter will not resume counting. When software triggering using the UEVG bit is selected as the STI source signal, there will be no clock pulse generated which can be used to make the counter resume counting. Note that the STI signal is only used to enable the counter to resume counting and has no effect on controlling the counter to stop counting.

STI source signal

(polarity=0)

STI source signal

(polarity=1)

STI

CK_CNT

CNT_EN

CNTR

(Up-counting)

TEVIF

27

Sync

28 29 30 31 32

Software clearing

Figure 122. GPTM in Trigger Mode

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Master Controller

The GPTMs and TMs can be linked together internally for timer synchronization or chaining.

When one GPTM is configured to be in the Master Mode, the GPTM Master Controller will generate a Master Trigger Output (MTO) signal which includes a reset, a start, a stop signal or a clock source which is selected by the MMSEL field in the MDCFR register to trigger or drive another GPTM or TM, if exists, which is configured in the Slave Mode.

GPTMn Master

MMSEL

TSE

MTO ITI

GPTMm/TMm Slave

SMSEL

TRSEL

Figure 123. Master GPTMn and Slave GPTMm/TMm Connection

The Master Mode Selection field, MMSEL, in the MDCFR register is used to select the MTO source for synchronizing another slave GPTM or TM if exists.

UEVG bit

Counter enable signal

Update Event

Channel 0 Capture/Compare event

CH0OREF

CH1OREF

CH2OREF

CH3OREF

MTO

MMSEL

Figure 124. MTO Selection

For example, setting the MMSEL field to 0x5 is to select the CH1OREF signal as the MTO signal to synchronize another slave GPTM or TM. For a more detailed description, refer to the related

MMSEL field definitions in the MDCFR register.

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Cortex ® -M0+ MCU

Channel Controller

The GPTM has four independent channels which can be used as capture inputs or compare match outputs. Each capture input or compare match output channel is composed of a preload register and a shadow register. Data access of the APB bus is always implemented by reading/writing the preload register.

When used in the input capture mode, the counter value is captured into the CHxCCR shadow register first and then transferred into the CHxCCR preload register when the capture event occurs.

When used in the compare match output mode, the contents of the CHxCCR preload register is copied into the associated shadow register, the counter value is then compared with the register value.

APB Bus Interface

CHxPSC

CHxCCR

(Preload Register)

Capture

Controller

Capture Transfer

Read CHxCCR

CHxCCR

(Shadow Register)

CHxCCS

CHxCCG

CHxE

Capture

Figure 125. Capture/Compare Block Diagram

Compare Transfer

Compare

Controller

CHxCCR

TM_CNT

CHxCCS

CHxPRE

Write CHxCCR

Update Event

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Cortex ® -M0+ MCU

Capture Counter Value Transferred to CHxCCR

When the channel is used as a capture input, the counter value is captured into the Channel

Capture/Compare Register (CHxCCR) when an effective input signal transition occurs. Once the capture event occurs, the CHxCCIF flag in the INTSR register is set accordingly. If the CHxCCIF bit is already set, i.e., the flag has not yet been cleared by software, and another capture event on this channel occurs, the corresponding channel Over-Capture flag, named CHxOCF, will be set.

f

CLKIN

GT_CH0

(TI0)

CNTR 25

CHxCCR 0

26

CHxCCIF

CHxOCF

Figure 126. Input Capture Mode

27 28

26

29 30 31 32 33

32

34 35

Pulse Width Measurement

The input capture mode can be also used for pulse width measurement from signals on the GT_

CHx pins, TIx. The following example shows how to configure the GPTM operated in the input capture mode to measure the high pulse width and the input period on the GT_CH0 pin using channel 0 and channel 1. The basic steps are shown as follows.

▆

▆

▆

▆

▆

▆

▆

Configure the capture channel 0 (CH0CCS = 0x1) to select the TI0 signal as the capture input.

Configure the CH0P bit to 0 to choose the rising edge of the TI0 input as the active polarity.

Configure the capture channel 1 (CH1CCS = 0x2) to select the TI0 signal as the capture input.

Configure the CH1P bit to 1 to choose the falling edge of the TI0 input as the active polarity.

Configure the TRSEL bits to 0x1 to select TI0S0 as the trigger input.

Configure the Slave controller to operate in the Restart mode by setting the SMSEL field in the

MDCFR register to 0x4.

Enable the input capture mode by setting the CH0E and CH1E bits in the CHCTR register to 1.

As the following diagram shows, the high pulse width on the GT_CH0 pin will be captured into the CH1CCR register while the input period will be captured into the CH0CCR register after input capture operation.

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Restart mode

Reset counter value

Restart mode

Reset counter value

GT_CH0

(TI0)

CNTR

7 0

Capture CH0

1 2 3 4 5

Capture CH1

6 7 0 1 2 3 4 5 6

CH0CCR

CH1CCR

Figure 127. PWM Pulse Width Measurement Example

7

4

Input Stage

The input stage consists of a digital filter, a channel polarity selection, edge detection and a channel prescaler. The channel 0 input signal (TI0) can be chosen to come from the GT_CH0 signal or the

Excusive-OR function of the GT_CH0, GT_CH1 and GT_CH2 signals. The channel input signal

(TIx) is sampled by a digital filter to generate a filtered input signal TIxFP. Then the channel polarity and the edge detection block can generate a TIxS0ED or TIxS1ED signal for the input capture function. The effective input event number can be set by the channel capture input source prescaler setting field, CHxPSC.

GT_CH0

GT_CH1

GT_CH2 f

XOR

TI0 sampling

TI0XOR

Filter

TI0F

TI0SRC f

CLKIN

TI0FP

TRCED

Edge

Detection

Edge

Detection f

CLKIN

TI0S0

TI0FN

CH0P

TI1S0

TI0S1

CH1P

TI1S1

GT_CH1 f

TI1 sampling

Filter

TI1FP

TI1F

TI1FN

Figure 128. Channel 0 and Channel 1 Input Stages

Edge

Detection

TI0S0ED

Edge

Detection

TI1S0ED

Edge

Detection

TI0S1ED

Edge

Detection

TI1S1ED

CH0CCS

CH1CCS

CH0PRESCALER

CH0PSC

CH1PRESCALER

CH1PSC

TI0BED

CH0PSC

CH0CAP Event

CH1PSC

CH1CAP Event

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GT_CH2

TI2 f sampling

Filter

TI2F

GT_CH3 f

TI3 sampling

Filter

TI3F

TI2FP

TI2FN

TRCED f

CLKIN

TI2S2

CH2P

TI3S2

TI3FP

TI3FN

TI2S3

CH3P

TI3S3

Edge

Detection

TI2S2ED

Edge

Detection

TI3S2ED

Edge

Detection

TI2S3ED

Edge

Detection

TI3S3ED

CH2CCS

CH2PRESCALER

CH2PSC

CH2PSC

CH2CAP Event

CH3PRESCALER

CH3PSC

CH3PSC

CH3CAP Event

CH3CCS

Figure 129. Channel 2 and Channel 3 Input Stages

Digital Filter

The digital filters are embedded in the input stage for the GT_CH0 ~ GT_CH3 pins respectively.

The digital filter in the GPTM is an N-event counter where N refers to how many valid transitions are necessary to output a filtered signal. The N value can be 0, 2, 4, 5, 6 or 8 according to the user selection for each filter by setting the TIxF field in the CHxICFR register.

Digital Filter (N=2)

No Filtered

TI0

D Q D Q D Q f

SYSTEM

CK CK f sampling

CK

Figure 130. TI0 Digital Filter Diagram with N = 2

J

CK

Q

K

Filtered

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Quadrature Decoder

The Quadrature Decoder function uses two quadrantal inputs TI0 and TI1 derived from the GT_CH0 and GT_CH1 pins respectively to interact to generate the counter value. The DIR bit is modified by hardware automatically during each input source transition. The input source can be either

TI0 only, TI1 only or both TI0 and TI1, the selection made by setting the SMSEL field to 0x1,

0x2 or 0x3. The mechanism for changing the counter direction is shown in the following table.

The Quadrature decoder can be regarded as an external clock with a directional selection. This means that the counter counts continuously in the interval between 0 and the counter-reload value.

Therefore, users must configure the CRR register before the counter starts to count.

TI0SRC f

CLKIN

TRCED

Edge

Detection

GT_CH0

GT_CH1

GT_CH2

XOR

TI0XOR

Edge

Detection

TI0 f sampling

Filter

TI0FP TI0FN f

CLKIN

TI0S0 Edge

Detection

TI0S0ED

CH0CCS

CH0P CH0PRESCALER

TI0F

TI1S0 Edge

Detection

TI1S0ED

CH0PSC

TI0S1

Edge

Detection

TI0S1ED

CH1P

CH1PRESCALER

GT_CH1

TI1 f sampling

Filter

TI1FP TI1FN

TI1S1 Edge

Detection

TI1S1ED

CH1PSC

TI1F

Figure 131. Input Stage and Quadrature Decoder Block Diagram

TI0S0

TI1S1

TI0S0ED

TI1S0ED

TI0S1ED

TI1S1ED

CH1CCS

Quadrature

Decoder

SMSEL

TI0BED

CH0PSC

CH0CAP Event

CH1PSC

CH1CAP Event

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Table 59. Counting Direction and Encoding Signals

Counting Mode

Counting on TI0 only

(SMSEL = 0x1)

Counting on TI1 only

(SMSEL = 0x2)

Counting on TI0 and TI1

(SMSEL = 0x3)

Level

TI1S1 = High

TI1S1 = Low

TI0S0 = High

TI0S0 = Low

TI1S1 = High

TI1S1 = Low

TI0S0 = High

TI0S0 = Low

Rising

TI0S0

Falling

Down Up

Up Down

—

—

Down

Up

X

X

—

—

Up

Down

X

X

Rising

TI1S1

Falling

— —

—

Up

Down

X

X

Up

Down

—

Down

Up

X

X

Down

Up

Note : “—” → means “no counting”; “X” → impossible

TI0

TI1

Up

Down

Quadrature Decoder

Counting on Both TI0 & TI1

(CH0P = 0, CH1P = 0)

Figure 132. Both TI0 and TI1 Quadrature Decoder Counting

Output Stage

The GPTM has four channels for compare match, single pulse or PWM output function. The channel output GT_CHxO is controlled by the CHxOM, CHxP and CHxE bits in the corresponding

CHxOCFR, CHPOLR and CHCTR registers.

CNTR

CHxCCR f

CLKIN

Output Mode

Controller

CHxOREF

CHxP

CHxOM x: 0 ~ 3

Figure 133. Output Stage Block Diagram

Output Enable

Controller

CHxE

GT_CHxO

CHxOREF

CHxCMP Event

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Channel Output Reference Signal

When the GPTM is used in the compare match output mode, the Channel x Output Reference signal, CHxOREF, is defined by the CHxOM field setup. The CHxOREF signal has several types of output function which defines what happens to the output when the counter value matches the contents of the CHxCCR register. In addition to the low, high and toggle CHxOREF output types, there are also PWM mode 1 and PWM mode 2 outputs. In these modes, the CHxOREF signal level is changed according to the count direction and the relationship between the counter value and the CHxCCR content. There are also two modes which will force the output into an inactive or active state irrespective of the CHxCCR content or counter values. With regard to a more detailed description refer to the relative bit definition. The accompanying Table 60 shows a summary of the output type setup.

Table 60. Compare Match Output Setup

CHxOM Value

0x0

0x1

No change

Clear Output to 0

Compare Match Level

0x2

0x3

0x4

0x5

0x6

0x7

Set Output to 1

Toggle Output

Force Inactive Level

Force Active Level

PWM Mode 1

PWM Mode 2

Counter Value

CRR

CHxCCR

(New value 2)

CHxCCR

(New value 3)

CHxCCR

(New value 1)

CHxCCR

Update

CHxCCR value

TME

CHxOREF

CHxOM=0x3, CHxPRE=0

(Output toggle, preload disable)

(1) (2) (3)

Time

Figure 134. Toggle Mode Channel Output Reference Signal (CHxPRE = 0)

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Counter Value

CRR

CHxCCR

(New value 2)

CHxCCR

(New value 3)

CHxCCR

(New value 1)

CHxCCR

Update

CHxCCR value

TME

CHxOREF

CHxOM=0x3, CHxPRE=1

(Output toggle, preload enable)

(1) (2) (3)


Time

Counter Value

CRR

CHxCCR

Counter Value

CHxCCR

CRR

Counter Value

CRR

CHxOM = 0x6 CHxCCR = 0x0000

100%

CHxOREF

CHxCCIF

CHxOREF CHxOREF 0%

CHxCCIF CHxCCIF

CHxOM = 0x7

CHxOREF

Figure 136. PWM Mode Channel Output Reference Signal and Counter in Up-counting Mode

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Counter Value

CRR

CHxCCR

Counter Value

CHxCCR

CRR

CHxOM = 0x6

CHxOREF

100%

CHxOREF

CHxCCIF

CHxOM = 0x7

CHxOREF

CHxCCIF

Figure 137. PWM Mode Channel Output Reference Signal and Counter in Down-counting Mode

CMSEL= 0x1

0

CHxCCR = 3

CHxCCIF

CHxCCR = 4

CHxCCIF

CHxCCR >= 5

CHxCCIF

1

Up-counting

2 3

100%

4

CRR = 5

5 4

Down-counting

3 2 1 0 1

CHxCCR = 0 0%

CHxCCIF

Figure 138. PWM Mode Channel Output Reference Signal and Counter in Centre-aligned Mode

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Update Management

The Update event is used to update the CRR, the PSCR, the CHxACR and the CHxCCR values from the actual registers to the corresponding shadow registers. An update event occurs when the counter overflows or underflows, the software update control bit is triggered or an update event from the slave controller is generated.

The UEVDIS bit in the CNTCFR register can determine whether the update event occurs or not. When the update event occurs, the corresponding update event interrupt will be generated depending upon whether the update event interrupt generation function is enabled or not by configuring the UGDIS bit in the CNTCFR register. For more detailed description, refer to the

UEVDIS and UGDIS bit definition in the CNTCFR register

Update Event Management

Counter Overflow / Underflow

UEVG

Slave Restart mode

UEV (Update PSCR, CRR,

CHxCCR, CHxACR

Shadow Registers)

UEVDIS

Update Event Interrupt Management


UEVG

Slave Restart mode

UGDIS

Figure 139. Update Event Setting Diagram

UEVDIS

UEV interrupt

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STI

CHxOREF

(PWM1)

(PWM2)

CHxOREF

(PWM1)

(PWM2)

Single Pulse Mode

Once the timer is set to operate in the single pulse mode, it is not necessary to set the timer enable bit TME in the CTR register to 1 to enable the counter. The trigger to generate a pulse can be sourced from the STI signal rising edge or by setting the TME bit to 1 using software. Setting the

TME bit to 1 or a trigger from the STI signal rising edge can generate a pulse and then keep the

TME bit at a high state until the update event occurs or the TME bit is written to 0 by software.

If the TME bit is cleared to 0 using software, the counter will be stopped and its value held. If the

TME bit is automatically cleared to 0 by a hardware update event, the counter will be reinitialized.

Counter Value

CRR

CHxCCR

Counter reinitialized Counter stopped and held

Time

TME bit

Triggered by STI

Cleared by

Update Event

Triggered by S/W Cleared by S/W delay delay min. delay min. delay delay delay delay delay

Flag is set by update event and cleared by S/W

CHxIMAE=0

CHxIMAE=1

UEVIF

CHxCCIF

Flag is set by compare match and cleared by S/W

Figure 140. Single Pulse Mode

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In the Single Pulse mode, the STI active edge which sets the TME bit to 1 will enable the counter.

However, there exist several clock delays to perform the comparison result between the counter value and the CHxCCR value. In order to reduce the delay to a minimum value, the user can set the CHxIMAE bit in each CHxOCFR register. After an STI rising edge trigger occurs in the single pulse mode, the CHxOREF signal will immediately be forced to the state which the CHxOREF signal will change to as the compare match event occurs without taking the comparison result into account. The CHxIMAE bit is available only when the output channel is configured to operate in the PWM mode 1 or PWM mode 2 and the trigger source is derived from the STI signal.

Counter Value

CKDIV = 0

CRR

Up-Counting Mode

6

5

CHxCCR

3

2

1

0

GT_CNT

ITIx

STI

TME

Counter Start Time

CHxIMAE

CHxOREF

(PWM1)

(PWM2)

Minimum delay

Figure 141. Immediate Active Mode Minimum Delay

4

Time

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Asymmetric PWM Mode

Asymmetric PWM mode allows two center-aligned PWM signals to be generated with a programmable phase shift. While the PWM frequency is determined by the value of the CRR register, the duty cycle and the phase-shift are determined by the CHxCCR and CHxACR register.

When the counter is counting up, the PWM uses the value in CHxCCR as up-count compare value.

When the counter is into counting down stage, the PWM uses the value in CHxACR as down-count compare value. The Figure 142 is shown as an example for asymmetric PWM mode in centeraligned counting mode.

Note: Asymmetric PWM mode can only be operated in center-aligned counting mode.

CNTR 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1

CRR = 8

PWM center-aligned mode

CRR = 8

CCR = 3, ACR = X

CCR = 3

CHxOREF


CRR = 8

CCR = 5, ACR = X

CCR = 5

CHxOREF

Asymmetric PWM center-aligned mode

CRR = 8

CCR = 3, ACR = 5

CCR = 3

ACR = 5

CHxOREF


CRR = 8

CCR = 5, ACR = 3

CCR = 5

ACR = 3

CHxOREF

Figure 142. Asymmetric PWM Mode versus Center-Aligned Counting Mode

Phase delay = 2

Timer Interconnection

The timers can be internally connected together for timer chaining or synchronization. This can be implemented by configuring one timer to operate in the Master mode while configuring another timer to be in the Slave mode. The following figures present several examples of trigger selection for the master and slave modes.

Using One Timer to Enable/Disable another Timer Start or Stop Counting

▆

Configure GPTM as the master mode to send its channel 0 Output Reference signal CH0OREF as a trigger output (MMSEL = 0x4).

▆

▆

▆

▆

▆

Configure GPTM CH0OREF waveform.

Configure PWM0 to receive its input trigger source from the GPTM trigger output (TRSEL = 0xA).

Configure PWM0 to operate in the pause mode (SMSEL = 0x5).

Enable PWM0 by writing ‘1’ to the TME bit.

Enable GPTM by writing ‘1’ to the TME bit.

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Master GPTM f

CLKIN

GPTM

CH0OREF

GPTM

CNTR

Slave PWM0

PWM0

CNTR

PWM0

TEVIF

32 33

FA

34

FB

35

Figure 143. Pausing PWM0 using the GPTM CH0OREF Signal

FC

36

Software clearing

00

FD

01

Using one Timer to Trigger another Timer Start Counting

▆

Configure GPTM to operate in the master mode to send its Update Event UEV as the trigger output (MMSEL = 0x2).

▆

Configure the GPTM period by setting the CRR register.

▆

▆

▆

Configure PWM0 to get the input trigger source from the GPTM trigger output (TRSEL = 0xA).

Configure PWM0 to be in the slave trigger mode (SMSEL = 0x6).

Start GPTM by writing ‘1’ to the TME bit.

f

CLKIN

GPTM

UEVIF

GPTM

CNTR 13 14 15 00

PWM0

CNTR

PWM0

TME bit

FA FB

PWM0

TEVIF

Software clearing

Figure 144. Triggering PWM0 with GPTM Update Event

01

FC

02

FD

03

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Starting Two Timers Synchronously in Response to an External Trigger

▆

Configure GPTM to operate in the master mode to send its enable signal as a trigger output

(MMSEL = 0x1).

▆

▆

▆

▆

▆

Configure GPTM slave mode to receive its input trigger source from GT_CH0 pin (TRSEL = 0x1).

Configure GPTM to be in the slave trigger mode (SMSEL = 0x6).

Enable the GPTM master timer synchronization function by setting the TSE bit in the MDCFR register to 1 to synchronize the slave timer.

Configure PWM0 to receive its input trigger source from the GPTM trigger output (TRSEL = 0xA).


Master GPTM f

DTS

=f

CLKIN

TI0

TI0FP

TI0S0ED

GPTM (TME bit)

GPTM (TEVIF)

GPTM CK_PSC

GPTM CNTR

TSE=1

Delay

34 0

Write UEVG bit

1

ITI

Slave PWM0

PWM0 (TME bit)

PWM0 (TEVIF)

PWM0 CK_PSC

PWM0 CNTR 11 0 0

Write UEVG bit

Figure 145. Trigger GPTM and PWM0 with the GPTM CH0 Input

1

2

2

3

3

4 5

4 5

Trigger Peripherals Start

To interconnect to the peripherals, such as ADC, Timer and so on, the GPTM could output the

MTO signal or the channel compare match output signal CHxOREF (x = 0 ~ 3) to be used as peripherals input trigger signal and depending on the MCU specification.

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PDMA Request

The GPTM supports the interface for PDMA data transfer. There are certain events which can generate the PDMA requests if the corresponding enable control bits are set to 1 to enable the

PDMA access. These events are the GPTM update events, trigger events and channel capture/ compare events. When the PDMA request is generated from the GPTM channel, it can be derived from the channel capture/compare event or the GPTM update event selected by the channel PDMA selection bit, CHCCDS, for all channels. For more detailed PDMA configuring information, refer to the corresponding section in the PDMA chapter.

CHCCDS

CH0_EV

UEV_EV

CH1_EV

UEV_EV

CH2_EV

UEV_EV

CH3_EV

UEV_EV

UEV_EV

UEVDE

TRIG_EV

TEVDE

Figure 146. GPTM PDMA Mapping Diagram

CH0CCDE

0

1

0

1

0

1

0

1

CH1CCDE

CH2CCDE

CH3CCDE

CH0 PDMA Request

CH1 PDMA Request

CH2 PDMA Request

CH3 PDMA Request

UEV PDMA Request

Trigger PDMA Request

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Register Map

The following table shows the GPTM registers and reset values.

Table 61. GPTM Register Map

Register

CNTCFR

MDCFR

TRCFR

Offset Description

0x000 Timer Counter Configuration Register

0x004 Timer Mode Configuration Register

0x008 Timer Trigger Configuration Register

INTSR

CNTR

PSCR

CRR

CH0CCR

CH1CCR

CH2CCR

CH3CCR

CH0ACR

CH1ACR

CH2ACR

CH3ACR

CTR

CH0ICFR

CH1ICFR

CH2ICFR

CH3ICFR

CH0OCFR

CH1OCFR

CH2OCFR

CH3OCFR

CHCTR

CHPOLR

DICTR

EVGR

0x010 Timer Control Register

0x020 Channel 0 Input Configuration Register



0x02C Channel 3 Input Configuration Register

0x040 Channel 0 Output Configuration Register



0x04C Channel 3 Output Configuration Register

0x050 Channel Control Register

0x054 Channel Polarity Configuration Register

0x074 Timer PDMA/Interrupt Control Register

0x078 Timer Event Generator Register

0x07C Timer Interrupt Status Register

0x080 Timer Counter Register

0x084 Timer Prescaler Register

0x088 Timer Counter-Reload Register

0x090 Channel 0 Capture/Compare Register



0x09C Channel 3 Capture/Compare Register

0x0A0 Channel 0 Asymmetric Compare Register



0x0AC Channel 3 Asymmetric Compare Register

Reset Value

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_FFFF

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

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Timer Counter Configuration Register – CNTCFR

This register specifies the GPTM counter configuration.

Offset: 0x000


31 30 29 27

Type/Reset

Type/Reset

Type/Reset

Type/Reset

Bits

[24]

[17:16]

[9:8]

23

15

Field

DIR

7

CMSEL

CKDIV

22

14

6

21

13

5

28

Reserved

20

Reserved

12

Reserved

4

Reserved

19

11

3

26

18

10

2

25 24

DIR

RW 0

17 16

CMSEL

RW 0 RW 0

9 8

CKDIV

RW 0 RW 0

1 0

UGDIS UEVDIS

RW 0 RW 0

Descriptions

Counting Direction

0: Count-up

1: Count-down

Note: This bit is read only when the Timer is configured to be in the Center-aligned mode or when used as a Quadrature decoder.

Counter Mode Selection

00: Edge-aligned mode. Normal up-counting and down-counting available for this mode. Counting direction is defined by the DIR bit.

01: Center-aligned mode 1. The counter counts up and down alternatively. The compare match interrupt flag is set during the count-down period.

10: Center-aligned mode 2. The counter counts up and down alternatively. The compare match interrupt flag is set during the count-up period.

11: Center-aligned mode 3. The counter counts up and down alternatively. The compare match interrupt flag is set during the count-up and count-down periods.

Clock Division

These two bits define the frequency ratio between the timer clock (f dead-time clock (f

DTS clock.

00: f

01: f

10: f

DTS

= f

DTS

= f

DTS

= f

CLKIN

CLKIN

/ 2

CLKIN

11: Reserved

/ 4

CLKIN

) and the

). The dead-time clock is also used for digital filter sampling

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Bits

[1]

[0]

Field

UGDIS

UEVDIS

Descriptions

Update event interrupt generation disable control

0: Any of the following events will generate an update PDMA request or interrupt

- Counter overflow/underflow

- Setting the UEVG bit

- Update generation through the slave mode

1: Only counter overflow/underflow generates an update PDMA request or interrupt

Update Event Disable control

0: Enable the update event request by one of following events:




1: Disable the update event (However the counter and the prescaler are reinitialized if the UEVG bit is set or if a hardware restart is received from the slave mode)

Timer Mode Configuration Register – MDCFR

This register specifies the GPTM master and slave mode selection and single pulse mode.

Offset: 0x004


Type/Reset

Type/Reset

Type/Reset

Type/Reset

31

23

15

7

30

22

14

6

29

21

Reserved

13

Reserved

5

28

Reserved

20

12

4

Reserved

27

19

11

3

26 25 24

SPMSET

RW 0

16 18 17

MMSEL

RW 0 RW 0 RW 0

10 9

SMSEL

8

RW 0 RW 0 RW 0

2 1 0

TSE

RW 0

Bits

[24]

Field

SPMSET

Descriptions

Single Pulse Mode Setting

0: Counter counts normally irrespective of whether the update event occurred or not

1: Counter stops counting at the next update event and then the TME bit is cleared by hardware

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Bits

[18:16]

Field

MMSEL

Descriptions

Master Mode Selection

Master mode selection is used to select the MTO signal source which is used to synchronize the other slave timer.

MMSEL [2:0] Mode

000

001

010

011

Reset Mode

Enable Mode

Update Mode

Capture/Compare

Mode

Descriptions

The MTO signal in the Reset mode is an output derived from one of the following cases:

1. Software setting UEVG bit

2. The STI trigger input signal which will be output on the MTO signal line when the Timer is used in the slave Restart mode

The Counter Enable signal is used as the trigger output.

The update event is used as the trigger output according to one of the following cases when the

UEVDIS bit is cleared to 0:

1. Counter overflow / underflow

2. Software setting UEVG

3. Slave trigger input when used in slave restart mode

When a Channel 0 capture or compare match event occurs, it will generate a positive pulse used as the master trigger output.

100

101

110

111

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Bits

[10:8]

[0]

Field

SMSEL

TSE

Descriptions

Slave Mode Selection

SMSEL [2:0] Mode

000

001

010

011

100

101

110

111

Disable Mode

Quadrature

Decoder Mode 1

Quadrature

Decoder Mode 2

Quadrature

Decoder Mode 3

Restart Mode

Pause Mode

Trigger Mode

STIED

Descriptions

The prescaler is clocked directly by the internal clock.

The counter uses the clock pulse generated from the interaction between the TI0 and TI1 signals to drive the counter prescaler. A transition of the TI0 edge is used in this mode depending upon the TI1 level.

The counter uses the clock pulse generated from the interaction between the TI0 and TI1 signals to drive the counter prescaler. A transition of the TI1 edge is used in this mode depending upon the TI0 level.

The counter uses the clock pulse generated from the interaction between the TI0 and TI1 signals to drive the counter prescaler. A transition of one channel edge is used in the quadrature decoder mode 3 depending upon the other channel level.

The counter value restarts from 0 or the CRR shadow register value depending upon the counter mode on the rising edge of the STI signal.

The registers will also be updated.

The counter starts to count when the selected trigger input STI is high. The counter stops counting on the instant, not being reset, when the

STI signal changes its state to a low level. Both the counter start and stop control are determined by the STI signal.

The counter starts to count from the original value in the counter on the rising edge of the selected trigger input STI. Only the counter start control is determined by the STI signal.

The rising edge of the selected trigger signal STI will clock the counter.

Timer Synchronization Enable

0: No action

1: Master timer (current timer) will generate a delay to synchronize its slave timer through the MTO signal.

Rev. 1.00 437 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Timer Trigger Configuration Register – TRCFR

This register specifies the trigger source selection of GPTM.

Offset: 0x008


31 30 29 28

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

21

13

5

Reserved

20

12

4

27

Reserved

19

Reserved

26

18

25

17

24

16

11

Reserved

10 9 8

3 2 1

TRSEL

0

RW 0 RW 0 RW 0 RW 0

Bits

[3:0]

Field

TRSEL

Descriptions

Trigger Source Selection

These bits are used to select the trigger input (STI) for counter synchronization.

0000: Software Trigger by setting the UEVG bit

0001: Filtered input of channel 0 (TI0S0)

0010: Filtered input of channel 1 (TI1S1)

0011: Reserved

1000: Channel 0 Edge Detector (TI0BED)

1001: Internal Timing Module Trigger 0 (ITI0)



Others: Reserved

Note: These bits must be updated only when they are not in use, i.e. the slave mode is disabled by setting the SMSEL field to 0x0.

Table 62. GPTM Internal Trigger Connection

Slave Timing Module

GPTM

ITI0

PWM0

ITI1

—

ITI2

PWM1

Rev. 1.00 438 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Timer Control Register – CTR

This register specifies the timer enable bit (TME), CRR buffer enable bit (CRBE) and Channel PDMA selection bit (CHCCDS).

Offset: 0x010


31 30 29 26 25 24

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

21

13

5

28

20

Reserved

27

Reserved

19

12

4

Reserved

11

Reserved

3

18

10

2

17

9

16

CHCCDS

RW 0

8

1

CRBE

0

TME

RW 0 RW 0

Bits

[16]

[1]

[0]

Field

CHCCDS

CRBE

TME

Descriptions

Channel PDMA event selection

0: Channel PDMA request derived from the channel capture/compare event.

1: Channel PDMA request derived from the Update event.

Counter-Reload register Buffer Enable

0: Counter-reload register can be updated immediately

1: Counter-reload register can not be updated until the update event occurs

Timer Enable bit

0: GPTM off

1: GPTM on – GPTM functions normally

When the TME bit is cleared to 0, the counter is stopped and the GPTM consumes no power in any operation mode except for the single pulse mode and the slave trigger mode. In these two modes the TME bit can automatically be set to 1 by hardware which permits all the GPTM registers to function normally.

Rev. 1.00 439 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Channel 0 Input Configuration Register – CH0ICFR

This register specifies the channel 0 input mode configuration.

Offset: 0x020


30 29 28 31

TI0SRC

Type/Reset RW 0

23

Type/Reset

15

Type/Reset

7

Type/Reset

22

14

6

21

Reserved

13

5

Reserved

20

12

4

27

Reserved

26 25 24

19 18

CH0PSC

17 16

CH0CCS

RW 0 RW 0 RW 0 RW 0

11

Reserved

10 9 8

3 2 1

TI0F

0

RW 0 RW 0 RW 0 RW 0

Bits

[31]

[19:18]

[17:16]

Field

TI0SRC

CH0PSC

CH0CCS

Descriptions

Channel 0 Input Source TI0 Selection

0: The GT_CH0 pin is connected to channel 0 input TI0

1: The XOR operation output of the GT_CH0, GT_CH1, and GT_CH2 pins are connected to the channel 0 input TI0

Channel 0 Capture Input Source Prescaler Setting

These bits define the effective events of the channel 0 capture input. Note that the prescaler is reset once the Channel 0 Capture/Compare Enable bit, CH0E, in the

Channel Control register named CHCTR is cleared to 0.

00: No prescaler, channel 0 capture input signal is chosen for each active event

01: Channel 0 Capture input signal is chosen for every 2 events



Channel 0 Capture/Compare Selection

00: Channel 0 is configured as an output

01: Channel 0 is configured as an input derived from the TI0 signal


11: Channel 0 is configured as an input which comes from the TRCED signal derived from the Trigger Controller

Note: The CH0CCS field can be accessed only when the CH0E bit is cleared to 0.

Rev. 1.00 440 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Bits

[3:0]

Field

TI0F

Descriptions

Channel 0 Input Source TI0 Filter Setting

These bits define the frequency divided ratio used to sample the TI0 signal. The

Digital filter in the GPTM is an N-event counter where N is defined as how many valid transitions are necessary to output a filtered signal.

0000: No filter, the sampling clock is f

SYSTEM

0001: f sampling

0010: f

0011: f

0100: f sampling sampling sampling

0101: f sampling

0110: f sampling

0111: f sampling

1000: f sampling

= f

= f

= f

= f

DTS

= f

= f

= f

CLKIN

CLKIN

CLKIN

DTS

DTS

DTS

= f

DTS

, N = 2

, N = 4

, N = 8

/ 2, N = 6

/ 2, N = 8

/ 4, N = 6

/ 4, N = 8

/ 8, N = 6

1001: f

1010: f

1011: f

1100: f sampling sampling sampling sampling

1101: f sampling

1110: f sampling

1111: f sampling

= f

= f

= f

= f

= f

DTS

= f

DTS

= f

DTS

DTS

DTS

DTS

DTS

/ 8, N = 8

/ 16, N = 5

/ 16, N = 6

/ 16, N = 8

/ 32, N = 5

/ 32, N = 6

/ 32, N = 8



Offset: 0x024


31 30 29 28

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

21

Reserved

13

5

Reserved

20

12

4

27

Reserved

26 25 24

19 18

CH1PSC

17 16

CH1CCS

RW 0 RW 0 RW 0 RW 0

11

Reserved

10 9 8

3 2 1

TI1F

0

RW 0 RW 0 RW 0 RW 0

Bits

[19:18]

Field

CH1PSC

Descriptions








Rev. 1.00 441 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Bits

[17:16]

[3:0]

Field

CH1CCS

TI1F

Descriptions











SYSTEM

0001: f sampling

0010: f

0011: f


0101: f sampling

0110: f sampling

0111: f sampling

1000: f sampling

= f

= f

= f

= f

DTS

= f

= f

= f

CLKIN

CLKIN

CLKIN

DTS

DTS

DTS

= f

DTS

, N = 2

, N = 4

, N = 8

/ 2, N = 6

/ 2, N = 8

/ 4, N = 6

/ 4, N = 8

/ 8, N = 6

1001: f

1010: f

1011: f


1101: f sampling

1110: f sampling

1111: f sampling

= f

= f

= f

= f

= f

DTS

= f

DTS

= f

DTS

DTS

DTS

DTS

DTS

/ 8, N = 8

/ 16, N = 5

/ 16, N = 6

/ 16, N = 8

/ 32, N = 5

/ 32, N = 6

/ 32, N = 8

Rev. 1.00 442 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU



Offset: 0x028


31 30 29 28

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

21

Reserved

13

5

Reserved

20

12

4

27

Reserved

26 25 24

19 18

CH2PSC

17 16

CH2CCS

RW 0 RW 0 RW 0 RW 0

11

Reserved

10 9 8

3 2 1

TI2F

0

RW 0 RW 0 RW 0 RW 0

Bits

[19:18]

[17:16]

Field

CH2PSC

CH2CCS

Descriptions














Rev. 1.00 443 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Bits

[3:0]

Field

TI2F

Descriptions





SYSTEM

0001: f sampling

0010: f

0011: f


0101: f sampling

0110: f sampling

0111: f sampling

1000: f sampling

= f

= f

= f

= f

DTS

= f

= f

= f

CLKIN

CLKIN

CLKIN

DTS

DTS

DTS

= f

DTS

, N = 2

, N = 4

, N = 8

/ 2, N = 6

/ 2, N = 8

/ 4, N = 6

/ 4, N = 8

/ 8, N = 6

1001: f

1010: f

1011: f


1101: f sampling

1110: f sampling

1111: f sampling

= f

= f

= f

= f

= f

DTS

= f

DTS

= f

DTS

DTS

DTS

DTS

DTS

/ 8, N = 8

/ 16, N = 5

/ 16, N = 6

/ 16, N = 8

/ 32, N = 5

/ 32, N = 6

/ 32, N = 8



Offset: 0x02C


31 30 29 28

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

21

Reserved

13

5

Reserved

20

12

4

27

Reserved

26 25 24

19 18

CH3PSC

17 16

CH3CCS

RW 0 RW 0 RW 0 RW 0

11

Reserved

10 9 8

3 2 1

TI3F

0

RW 0 RW 0 RW 0 RW 0

Bits

[19:18]

Field

CH3PSC

Descriptions








Rev. 1.00 444 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Bits

[17:16]

[3:0]

Field

CH3CCS

TI3F

Descriptions











SYSTEM

0001: f sampling

0010: f

0011: f


0101: f sampling

0110: f sampling

0111: f sampling

1000: f sampling

= f

= f

= f

= f

DTS

= f

= f

= f

CLKIN

CLKIN

CLKIN

DTS

DTS

DTS

= f

DTS

, N = 2

, N = 4

, N = 8

/ 2, N = 6

/ 2, N = 8

/ 4, N = 6

/ 4, N = 8

/ 8, N = 6

1001: f

1010: f

1011: f


1101: f sampling

1110: f sampling

1111: f sampling

= f

= f

= f

= f

= f

DTS

= f

DTS

= f

DTS

DTS

DTS

DTS

DTS

/ 8, N = 8

/ 16, N = 5

/ 16, N = 6

/ 16, N = 8

/ 32, N = 5

/ 32, N = 6

/ 32, N = 8

Rev. 1.00 445 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Channel 0 Output Configuration Register – CH0OCFR

This register specifies the channel 0 output mode configuration.

Offset: 0x040


31

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

30

22

29

21

28

20

27

Reserved

19

Reserved

26

18

25

17

24

16

14 13 12 11

Reserved

6 5 4 3

Reserved CH0IMAE CH0PRE Reserved

RW 0 RW 0

10

2

9

1

CH0OM[2:0]

8

CH0OM[3]

RW 0

0

RW 0 RW 0 RW 0

Bits

[5]

[4]


CH0IMAE Channel 0 Immediate Active Enable

0: No action

1: Single pulse Immediate Active Mode is enabled

The CH0OREF signal will be forced to the compare matched level immediately after an available trigger event occurs irrespective of the result of the comparison between the CNTR and the CH0CCR values.

The effective duration ends automatically at the next overflow or underflow event.

Note: The CH0IMAE bit is available only if the channel 0 is configured to be operated in the PWM mode 1 or PWM mode 2.

CH0PRE Channel 0 Capture/Compare Register (CH0CCR) Preload Enable

0: CH0CCR preload function is disabled

The CH0CCR register can be immediately assigned a new value when the CH0PRE bit is cleared to 0 and the updated CH0CCR value is used immediately.

1: CH0CCR preload function is enabled

The new CH0CCR value will not be transferred to its shadow register until the update event occurs.

Rev. 1.00 446 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Bits

[8][2:0]


CH0OM[3:0] Channel 0 Output Mode Setting

These bits define the functional types of the output reference signal CH0OREF.

0000: No Change

0001: Output 0 on compare match


0011: Output toggles on compare match

0100: Force inactive – CH0OREF is forced to 0

0101: Force active – CH0OREF is forced to 1

0110: PWM mode 1

- During up-counting, channel 0 has an active level when CNTR <

CH0CCR or otherwise has an inactive level.

- During down-counting, channel 0 has an inactive level when CNTR >

CH0CCR or otherwise has an active level.

0111: PWM mode 2

- During up-counting, channel 0 is has an inactive level when CNTR <


- During down-counting, channel 0 has an active level when CNTR >


1110: Asymmetric PWM mode 1




CH0ACR or otherwise has an active level.


- During up-counting, channel 0 has an inactive level when CNTR <



CH0ACR or otherwise has an inactive level

Note: When channel 0 is used as asymmetric PWM output mode, the Counter Mode

Selection bit in Counter Configuration Register must be configured as Centeraligned Counting mode (CMSEL = 0x1/0x2/0x3).

Rev. 1.00 447 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU



Offset: 0x044


31

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

30

22

29

21

28

20

27

Reserved

19

Reserved

26

18

25

17

24

16

14 13 12 11

Reserved

6 5 4 3


RW 0 RW 0

10

2

9

1

CH1OM[2:0]

8

CH1OM[3]

RW 0

0

RW 0 RW 0 RW 0

Bits

[5]

[4]



0: No action






0: CH1CCR preload function is disabled.




Rev. 1.00 448 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Bits

[8][2:0]




0000: No Change






0110: PWM mode 1





0111: PWM mode 2

















Rev. 1.00 449 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU



Offset: 0x048


31

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

30

22

29

21

28

20

27

Reserved

19

Reserved

26

18

25

17

24

16

14 13 12 11

Reserved

6 5 4 3


RW 0 RW 0

10

2

9

1

CH2OM[2:0]

8

CH2OM[3]

RW 0

0

RW 0 RW 0 RW 0

Bits

[5]

[4]



0: No action










Rev. 1.00 450 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Bits

[8][2:0]




0000: No Change






0110: PWM mode 1





0111: PWM mode 2

















Rev. 1.00 451 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU



Offset: 0x04C


31

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

30

22

29

21

28

20

27

Reserved

19

Reserved

26

18

25

17

24

16

14 13 12 11

Reserved

6 5 4 3


RW 0 RW 0

10

2

9

1

CH3OM[2:0]

8

CH3OM[3]

RW 0

0

RW 0 RW 0 RW 0

Bits

[5]

[4]



0: No action










Rev. 1.00 452 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Bits

[8][2:0]



These bits define the functional types of the output reference signal CH3OREF

0000: No Change






0110: PWM mode 1





0111: PWM mode 2




CH3CCR or otherwise has an inactive level













Rev. 1.00 453 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Channel Control Register – CHCTR

This register contains the channel capture input or compare output function enable control bits.

Offset: 0x050


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

Type/Reset

Type/Reset

15 14 13 12 11

Reserved

10 9 8

7

Reserved

6

CH3E

RW 0

5

Reserved

4

CH2E

RW 0

3

Reserved

2

CH1E

RW 0

1

Reserved

0

CH0E

RW 0

Bits

[6]

[4]

[2]

Field

CH3E

CH2E

CH1E

Descriptions

Channel 3 Capture/Compare Enable

- Channel 3 is configured as an input (CH3CCS = 0x1/0x2/0x3)

0: Input Capture Mode is disabled

1: Input Capture Mode is enabled

- Channel 3 is configured as an output (CH3CCS = 0x0)

0: Off – Channel 3 output signal CH3O is not active

1: On – Channel 3 output signal CH3O is generated on the corresponding output pin















Rev. 1.00 454 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Bits

[0]

Field

CH0E

Descriptions








Channel Polarity Configuration Register – CHPOLR

This register contains the channel capture input or compare output polarity control.

Offset: 0x054


Type/Reset

31

23

30

22

29

21

28

20

27

Reserved

19

Reserved

26

18

25

17

24

16

Type/Reset

Type/Reset

Type/Reset

15 14 13 12 11

Reserved

10 9 8

7

Reserved

6

CH3P

RW 0

5

Reserved

4

CH2P

RW 0

3

Reserved

2

CH1P

RW 0

1

Reserved

0

CH0P

RW 0

Bits

[6]

[4]

Field

CH3P

CH2P

Descriptions

Channel 3 Capture/Compare Polarity

- When Channel 3 is configured as an input (CH3CCS = 0x1/0x2/0x3)

0: capture event occurs on a Channel 3 rising edge

1: capture event occurs on a Channel 3 falling edge

- When Channel 3 is configured as an output (CH3CCS = 0x0)

0: Channel 3 Output is active high

1: Channel 3 Output is active low








Rev. 1.00 455 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Bits

[2]

[0]

Field

CH1P

CH0P

Descriptions















Timer PDMA/Interrupt Control Register – DICTR

This register contains the timer PDMA and interrupt enable control bits.

Offset: 0x074


Type/Reset

Type/Reset

Type/Reset

Type/Reset

31

23

15

7

30

22

14

6

29

Reserved

21

Reserved

13

Reserved

5

Reserved

28

20

12

4

27 26 25 24

TEVDE Reserved UEVDE

19

RW 0

18 17

RW 0

16

CH3CCDE CH2CCDE CH1CCDE CH0CCDE

RW 0 RW 0 RW 0 RW 0

11 10 9 8

TEVIE

RW 0

Reserved UEVIE

RW 0

3 2 1 0

CH3CCIE CH2CCIE CH1CCIE CH0CCIE

RW 0 RW 0 RW 0 RW 0

Bits

[26]

[24]

[19]

[18]


TEVDE

UEVDE

Trigger event PDMA Request Enable

0: Trigger PDMA request is disabled

1: Trigger PDMA request is enabled

Update event PDMA Request Enable

0: Update event PDMA request is disabled

1: Update event PDMA request is enabled

CH3CCDE Channel 3 Capture/Compare PDMA Request Enable

0: Channel 3 PDMA request is disabled

1: Channel 3 PDMA request is enabled




Rev. 1.00 456 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Bits

[17]

[2]

[1]

[0]

[8]

[3]

[16]

[10]








TEVIE Trigger event Interrupt Enable

0: Trigger event interrupt is disabled

1: Trigger event interrupt is enabled

UEVIE

CH3CCIE

Update event Interrupt Enable

0: Update event interrupt is disabled

1: Update event interrupt is enabled

Channel 3 Capture/Compare Interrupt Enable

0: Channel 3 interrupt is disabled

1: Channel 3 interrupt is enabled

CH2CCIE

CH1CCIE

CH0CCIE










Rev. 1.00 457 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Timer Event Generator Register – EVGR

This register contains the software event generation bits.

Offset: 0x078


31 30 29 28

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

21

13

Reserved

5

Reserved

20

12

4

27

Reserved

19

Reserved

26

18

25

17

24

16

11 10

TEVG

9

Reserved

8

UEVG

3

WO 0

2 1

WO 0

0

CH3CCG CH2CCG CH1CCG CH0CCG

WO 0 WO 0 WO 0 WO 0

Bits

[10]

[8]

[3]

[2]

Field

TEVG

UEVG

CH3CCG

CH2CCG

Descriptions

Trigger Event Generation

The trigger event TEV can be generated by setting this bit. It is cleared by hardware automatically.

0: No action

1: TEVIF flag is set

Update Event Generation

The update event UEV can be generated by setting this bit. It is cleared by hardware automatically.

0: No action

1: Reinitialize the counter

The counter value returns to 0 or the CRR preload value, depending on the counter mode in which the current timer is being used. An update operation of any related registers will also be performed. For more detailed descriptions, refer to the corresponding section.

Channel 3 Capture/Compare Generation

A Channel 3 capture/compare event can be generated by setting this bit. It is cleared by hardware automatically.

0: No action

1: Capture/compare event is generated on channel 3

If Channel 3 is configured as an input, the counter value is captured into the

CH3CCR register and then the CH3CCIF bit is set. If Channel 3 is configured as an output, the CH3CCIF bit is set.



0: No action




Rev. 1.00 458 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Bits

[1]

[0]

Field

CH1CCG

CH0CCG

Descriptions



0: No action






0: No action




Timer Interrupt Status Register – INTSR

This register stores the timer interrupt status.

Offset: 0x07C


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

Type/Reset

15 14 13

Reserved

12 11 10

TEVIF

W0C 0

9

Reserved

8

UEVIF

W0C 0

7 6 5 4 3 2 1 0

CH3OCF CH2OCF CH1OCF CH0OCF CH3CCIF CH2CCIF CH1CCIF CH0CCIF

Type/Reset W0C 0 W0C 0 W0C 0 W0C 0 W0C 0 W0C 0 W0C 0 W0C 0

Bits

[10]

Field

TEVIF

Descriptions

Trigger Event Interrupt Flag

This flag is set by hardware on a trigger event and is cleared by software.

0: No trigger event occurs

1: Trigger event occurs

Rev. 1.00 459 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Bits

[8]

[7]

[6]

[5]

[4]

[3]

[2]

Field

UEVIF

CH3OCF

CH2OCF

CH1OCF

CH0OCF

CH3CCIF

CH2CCIF

Descriptions

Update Event Interrupt Flag

This bit is set by hardware on an update event and is cleared by software.

0: No update event occurs

1: Update event occurs

Note: The update event is derived from the following conditions:

- The counter overflows or underflows

- The UEVG bit is asserted

- A restart trigger event occurs from the slave trigger input

Channel 3 Over-Capture Flag

This flag is set by hardware and cleared by software.

0: No over-capture event is detected

1: Capture event occurs again when the CH3CCIF bit is already set and it is not yet cleared by software




1: Capture event occurs again when the CH2CCIF bit is already set and it is not cleared yet by software




1: Capture event occurs again when the CH1CCIF bit is already set and it is not cleared yet by software.




1: Capture event occurs again when the CH0CCIFbit is already set and it is not yet cleared by software.

Channel 3 Capture/Compare Interrupt Flag

- Channel 3 is configured as an output:

0: No match event occurs

1: The content of the counter CNTR has matched the content of the CH3CCR register

This flag is set by hardware when the counter value matches the CH3CCR value except in the center-aligned mode. It is cleared by software.

- Channel 3 is configured as an input:

0: No input capture occurs

1: Input capture occurs

This bit is set by hardware on a capture event. It is cleared by software or by reading the CH3CCR register.








1: Input capture occurs.


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HT32F5828

Cortex ® -M0+ MCU

Bits

[1]

[0]

Field

CH1CCIF

CH0CCIF

Descriptions



















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Cortex ® -M0+ MCU

Timer Counter Register – CNTR

This register stores the timer counter value.

Offset: 0x080


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

CNTV

10 9 8


7 6 5 4 3 2 1 0

CNTV


Bits

[15:0]

Field

CNTV

Descriptions

Counter Value

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Cortex ® -M0+ MCU

Timer Prescaler Register – PSCR

This register specifies the timer prescaler value to generate the counter clock.

Offset: 0x084


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

PSCV

10 9 8


7 6 5 4 3 2 1 0

PSCV


Bits

[15:0]

Field

PSCV

Descriptions

Prescaler Value

These bits are used to specify the prescaler value to generate the counter clock frequency f

CK_CNT

.

f

CK_CNT

= f

CK_PSC

PSCV[15:0]+1

, where the f

CK_PSC

is the prescaler clock source.

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Cortex ® -M0+ MCU

Timer Counter-Reload Register – CRR

This register specifies the timer counter-reload value.

Offset: 0x088

Reset value: 0x0000_FFFF

31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

CRV

10 9 8


7 6 5 4 3 2 1 0

CRV


Bits

[15:0]

Field

CRV

Descriptions

Counter-Reload Value

The CRV is the reload value which is loaded into the actual counter register.

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Cortex ® -M0+ MCU

Channel 0 Capture/Compare Register – CH0CCR

This register specifies the timer channel 0 capture/compare value.

Offset: 0x090


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

CH0CCV

10 9 8


7 6 5 4 3 2 1 0

CH0CCV


Bits

[15:0]

Field

CH0CCV

Descriptions

Channel 0 Capture/Compare Value

- When Channel 0 is configured as an output:

The CH0CCR value is compared with the counter value and the comparison result is used to trigger the CH0OREF output signal.

- When Channel 0 is configured as an input:

The CH0CCR register stores the counter value captured by the last channel 0 capture event.

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Offset: 0x094


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

CH1CCV

10 9 8


7 6 5 4 3 2 1 0

CH1CCV


Bits

[15:0]

Field

CH1CCV

Descriptions






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Cortex ® -M0+ MCU



Offset: 0x098


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

CH2CCV

10 9 8


7 6 5 4 3 2 1 0

CH2CCV


Bits

[15:0]

Field

CH2CCV

Descriptions






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Offset: 0x09C


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

CH3CCV

10 9 8


7 6 5 4 3 2 1 0

CH3CCV


Bits

[15:0]

Field

CH3CCV

Descriptions






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Cortex ® -M0+ MCU

Channel 0 Asymmetric Compare Register – CH0ACR

This register specifies the timer channel 0 asymmetric compare value.

Offset: 0x0A0


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

CH0ACV

10 9 8


7 6 5 4 3 2 1 0

CH0ACV


Bits

[15:0]

Field

CH0ACV

Descriptions

Channel 0 Asymmetric Compare Value

When channel 0 is configured as asymmetric PWM mode and the counter is counting down, the value written into this register will be compared to the counter.



Offset: 0x0A4


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

CH1ACV

10 9 8


7 6 5 4 3

CH1ACV

2 1 0


Bits

[15:0]

Field

CH1ACV

Descriptions



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Cortex ® -M0+ MCU



Offset: 0x0A8


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

CH2ACV

10 9 8


7 6 5 4 3 2 1 0

CH2ACV


Bits

[15:0]

Field

CH2ACV

Descriptions





Offset: 0x0AC


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

CH3ACV

10 9 8


7 6 5 4 3

CH3ACV

2 1 0


Bits

[15:0]

Field

CH3ACV

Descriptions



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ITI0

ITI1

ITI2

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

23

Pulse-Width-Modulation Timer (PWM)

Introduction

The Pulse-Width-Modulation Timer consists of one 16-bit up/down-counter, four 16-bit Compare

Registers (CRs), one 16-bit Counter-Reload Register (CRR) and several control/status registers. It can be used for a variety of purposes including general timer and output waveform generation such as single pulse generation or PWM output.

f

CLKIN

Edge

Detector

STIED

STI

Clock

Controller

TEV UEVG

TME

UEV

CHxOREF

(x = 0 ~ 3)

MDCFR

Register

Slave

Controller

Master

Controller

MTO To other Timers,

ADC and so on

TEV : Trigger Event

MEVx : Channel x Compare Match Event

UEV : Update Event

CK_PSC PSC

PRESCALER

CK_CNT

Restart

Pause

Trigger

Up/Down

TM_CNT

Reload

Register

(CRR)

UEV

CH0 Compare Register

(CH0CR)

MEV0

CH0OREF


(CH1CR)

MEV1

CH1OREF


(CH2CR)

MEV2

CH2OREF


(CH3CR)

MEV3

CH3OREF

Figure 147. PWM Block Diagram

Output

Control

Output

Control

Output

Control

Output

Control

PWM_CH0

PWM_CH1

PWM_CH2

PWM_CH3

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Cortex ® -M0+ MCU

Features

▆

▆

▆

▆

▆

▆

16-bit up/down auto-reload counter

16-bit programmable prescaler that allows division of the prescaler clock source by any factor between 1 and 65536 to generate the counter clock frequency

Up to 4 independent channels for:


● Generation of PWM waveform - Edge and Center-aligned Mode

● Single Pulse Mode Output

Synchronization circuit to control the timer with external signals and to interconnect several timers together

Interrupt/PDMA generation with the following events:

● Update event

● Trigger event

● Output compare match event

PWM Master/Slave mode controller


Counter Mode

Up-Counting

In this mode the counter counts continuously from 0 to the counter-reload value, which is defined in the CRR register, in a count-up direction. Once the counter reaches the counter-reload value, the Timer Module generates an overflow event and the counter restarts to count once again from

0. This action will continue repeatedly. The counting direction bit DIR in the CNTCFR register should be set to 0 for the up-counting mode.

When the update event is generated by setting the UEVG bit in the EVGR register to 1, the counter value will also be initialized to 0.

CK_PSC

CNT_EN

CK_CNT

CNTR

CRR

CRR Shadow

Register

PSCR

PSCR Shadow

Register

PSC_CNT

Counter Overflow

Update Event Flag

F5

F2

0

F5

0

0

F3

Write a new value


F4 F5

0

0


1

36

0

1

1

1

36

1

0

2

1

Software clearing

0

3

1

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Cortex ® -M0+ MCU

Down-Counting

In this mode the counter counts continuously from the counter-reload value, which is defined in the CRR register, to 0 in a count-down direction. Once the counter reaches 0, the Timer module generates an underflow event and the counter restarts to count once again from the counter-reload value. This action will continue repeatedly. The counting direction bit DIR in the CNTCFR register should be set to 1 for the down-counting mode.

When the update event is set by the UEVG bit in the EVGR register, the counter value will also be initialized to the counter-reload value.

CK_PSC

CNT_EN

CK_CNT

CNTR

CRR

CRR Shadow

Register

PSCR

PSCR Shadow

Register

PSC_CNT

Counter Underflow

Update Event Flag

F5

3

0

F5

0

0

2

Write a new value

Figure 149. Down-counting Example

1 0

0

36

Update a new value

1

36

0

35

1

1

36

1

0

34

Software clearing

1

33

0 1

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Cortex ® -M0+ MCU

Center-Aligned Counting

In the center-aligned counting mode, the counter counts up from 0 to the counter-reload value and then counts down to 0 alternatively. The Timer module generates an overflow event when the counter counts to the counter-reload value in the up-counting mode and generates an underflow event when the counter counts to 0 in the down-counting mode. The counting direction bit DIR in the CNTCFR register is read-only and indicates the counting direction when in the center-aligned mode. The counting direction is updated by hardware automatically.

Setting the UEVG bit in the EVGR register will initialize the counter value to 0 irrespective of whether the counter is counting up or down in the center-aligned counting mode.

The update event interrupt flag bit in the INTSR register will be set to 1, when an overflow or underflow event occurs.

CK_PSC

CNT_EN

CK_CNT

CNTR

CRR

CRR Shadow

Register

Counter Overflow

Counter Underflow

Update Event Flag

F2

F5

F5

F3 F4 4

Write a new value

Figure 150. Center-aligned Counting Example

3 2

Software clearing

4

1

4

0 1 2

Software clearing

3

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▆


CLKIN

:


CLKIN

used to drive the counter prescaler.

▆

STIED:




PSCR CRR f

CLKIN

(Internal APB clock) Update Event

STIED

(Trigger events)

CK_PSC

CLK

PSC Prescaler

Reset

CK_CNT

CLK

CNTR

Reset

TM_CNT

TRSEL

SMSEL

Start/Stop

Figure 151. PWM Clock Source Selection

Overflow /

Underflow UEVG bit


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The trigger controller is used to select the trigger source and setup the trigger level or edge trigger condition. For the internal trigger input, it can be selected by the Trigger Selection bits TRSEL in the TRCFR register. For all the trigger sources except the UEVG bit software trigger, the internal edge detection circuitry will generate a clock pulse at each trigger signal rising edge to stimulate some PWM functions which are triggered by a trigger signal rising edge.

Trigger Controller Block = Edge Trigger Mux + Level Trigger Mux

Internal Trigger Input

ITI0

ITI1

ITI2

Edge Detection

ITI0ED

ITI1ED

ITI2ED f

CLKIN

Edge Trigger Source = Internal (ITIx)


Reserved

ITI0ED

ITI1ED

ITI2ED

Reserved

0000

1001

1010

1011 others

TRSEL[3:0]

STIED

Level Trigger Source = Internal (ITIx) + Software UEVG bit


S/W Set UEVG Bit

ITI0

ITI1

ITI2

Reserved

0000

1001

1010

1011 others

TRSEL[3:0]


STI

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The PWM can be synchronized with an external trigger in several modes including the Restart mode, the Pause mode and the Trigger mode which is selected by the SMSEL field in the MDCFR register. The trigger input of these modes comes from the STI signal which is selected by the

TRSEL field in the TRCFR register. The operation modes in the Slave Controller are described in the accompanying sections.

Trigger Controller

STI

Slave

Controller

Trigger Event


SMSEL Restart/Pause/Trigger Mode


Restart Mode




STI source signal

(polarity=0)

STI source signal

(polarity=1)

STI

CK_CNT

UEVG bit

(reset counter)

CNTR

(Up-counting)

CNTR

(Down-counting)

TEVIF

27

27

28

26

29

25

Figure 154. PWM in Restart Mode

Sync.

30

24

31

23

Trigger Event

0

32

1

31

2

30

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Pause Mode

In the Pause Mode, the selected STI input signal level is used to control the counter start/stop operation. The counter starts to count when the selected STI signal is at a high level and stops counting when the STI signal is changed to a low level, here the counter will maintain its present value and will not be reset. Since the Pause function depends upon the STI level to control the counter stop/start operation.

STI source signal

(polarity=0)

STI source signal

(polarity=1)

STI

CK_ CNT

CNT_ EN

CNTR

TEVIF

Sync

27 28 29

Sync

30 31

Software clearing

Figure 155. PWM in Pause Mode

Trigger Mode


STI source signal

(polarity=0)

STI source signal

(polarity=1)

STI

CK_CNT

CNT_EN

CNTR

(Up-counting)

TEVIF

27

Sync

28 29 30 31 32

Software clearing

Figure 156. PWM in Trigger Mode

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Master Controller

The PWMs and TMs can be linked together internally for timer synchronization or chaining. When one PWM is configured to be in the Master Mode, the PWM Master Controller will generate a

Master Trigger Output (MTO) signal which includes a reset, a start, a stop signal or a clock source which is selected by the MMSEL field in the MDCFR register to trigger or drive another PWM or

TM, if exists, which is configured in the Slave Mode.

PWMn Master

MMSEL

TSE

MTO ITI

PWMm/TMm Slave

SMSEL

TRSEL

Figure 157. Master PWMn and Slave PWMm/TMm Connection

The Master Mode Selection bits, MMSEL, in the MDCFR register are used to select the MTO source for synchronizing another slave PWM or TM if exists.

UEVG bit

Counter enable signal

Update Event

CH0OREF

CH1OREF

CH2OREF

CH3OREF

MTO

MMSEL

Figure 158. MTO Selection

For example, setting the MMSEL field to 0x5 is to select the CH1OREF signal as the MTO signal to synchronize another slave PWM or TM. For a more detailed description, refer to the related

MMSEL field definitions in the MDCFR register.

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Cortex ® -M0+ MCU


The PWM has four independent channels which can be used as compare match outputs. Each compare match output channel is composed of a preload register and a shadow register. Data access of the APB bus is always implemented by reading/writing preload register.

When used in the compare match output mode, the contents of the CHxCR preload register is copied into the associated shadow register; the counter value is then compared with the register value.

APB Bus Interface

CHxCR

(Preload Register)

Compare Transfer

CHxCR

(Shadow Register)

Compare

Controller

Write CHxCR

Update Event

CNTR CHxPRE

Figure 159. Compare Block Diagram

Output Stage

The PWM has four channels for compare match, single pulse or PWM output function. The channel output PWM_CHx is controlled by the CHxOM, CHxP and CHxE bits in the corresponding

CHxOCFR, CHPOLR and CHCTR registers.

CNTR

CHxCR f

CLKIN

Output Mode

Controller x: 0 ~ 3

CHxOM


CHxOREF

CHxP

Output Enable

Controller

CHxE

PWM_CHx

CHxOREF

CHxCMP Event

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Cortex ® -M0+ MCU


When the PWM is used in the compare match output mode, the Channel x Output Reference signal,

CHxOREF, is defined by the CHxOM field setup. The CHxOREF signal has several types of output function which defines what happens to the output when the counter value matches the contents of the CHxCR register. In addition to the low, high and toggle CHxOREF output types; there are also

PWM mode 1 and PWM mode 2 outputs. In these modes, the CHxOREF signal level is changed according to the count direction and the relationship between the counter value and the CHxCR content. There are also two modes which will force the output into an inactive or active state irrespective of the CHxCR content or counter values. With regard to a more detailed description refer to the relative bit definition. The accompanying Table 63 shows a summary of the output type setup.


CHxOM Value

0x0

0x1

No change

Clear Output to 0


0x2

0x3

0x4

0x5

0x6

0x7

0xE

0xF

Set Output to 1

Toggle Output


Force Active Level

PWM Mode 1

PWM Mode 2

Asymmetric PWM mode 1

Asymmetric PWM mode 2

Counter Value

CRR

CHxCR

(New value 2)

CHxCR

(New value 3)

CHxCR

(New value 1)

CHxCR

Update

CHxCR value

TME

CHxOREF

CHxOM=0x3, CHxPRE=0


(1) (2) (3)

Time


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Counter Value

CRR

CHxCR

(New value 2)

CHxCR

(New value 3)

CHxCR

(New value 1)

CHxCR

Update

CHxCR value

TME

CHxOREF

CHxOM=0x3, CHxPRE=1


(1) (2) (3)


Time

Counter Value

CRR

CHxCR

Counter Value

CHxCR

CRR

Counter Value

CRR

CHxOM = 0x6 CHxCR = 0x0000

100%

CHxOREF

CHxCIF

CHxOM = 0x7

CHxOREF

CHxOREF

CHxCIF

CHxOREF

CHxCIF

0%

Figure 163. PWM Mode Channel Output Reference Signal and Counter in Up-counting Mode

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Counter Value

CRR

CHxCR

Counter Value

CHxCR

CRR

CHxOM = 0x6

CHxOREF CHxOREF

100%

CHxCIF

CHxOM = 0x7

CHxOREF

CHxCIF

Figure 164. PWM Mode Channel Output Reference Signal and Counter in Down-counting Mode

CMSEL= 0x1

0

CHxCR = 3

CHxCIF

CHxCR = 4

CHxCIF

CHxCR >= 5

CHxCIF

1

Up-counting

2 3

100%

4

CRR = 5

5 4

Down-counting

3 2 1 0 1

CHxCR = 0

0%

CHxCIF

Figure 165. PWM Mode Channel Output Reference Signal and Counter in Center-aligned Mode

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The Update event is used to update the CRR, the PSCR, the CHxACR and the CHxCR values from the actual registers to the corresponding shadow registers. An update event occurs when the counter overflows or underflows, the software update control bit is triggered or an update event from the slave controller is generated.


UEVDIS and UGDIS bit definition in the CNTCFR register.



UEVG

Slave Restart mode


CHxCR, CHxACR

Shadow Registers)

UEVDIS



UEVG

Slave Restart mode

UGDIS


UEVDIS

UEV interrupt

Single Pulse Mode

Once the timer is set to operate in the single pulse mode, it is not necessary to set the timer enable bit TME in the CTR register to 1 to enable the counter. The trigger to generate a pulse can be sourced from the STI signal rising edge or by setting the TME bit to 1 using software. Setting the

TME bit to 1 or a trigger from the STI signal rising edge can generate a pulse and then keep the

TME bit at a high state until the update event occurs or the TME bit is written to 0 by software.

If the TME bit is cleared to 0 using software, the counter will be stopped and its value held. If the

TME bit is automatically cleared to 0 by a hardware update event, the counter will be reinitialized.

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TME bit

STI

CHxOREF

(PWM1)

(PWM2)

CHxOREF

(PWM1)

(PWM2)

UEVIF

CHxCIF

Counter Value

CRR

CHxCR

Counter reinitialized Counter stopped and held

Time

Triggered by STI

Cleared by

Update Event

Triggered by S/W Cleared by S/W delay delay min. delay min. delay delay delay delay

Flag is set by update event and cleared by S/W delay

CHxIMAE=0

CHxIMAE=1

Flag is set by compare match and cleared by S/W

Figure 167. Single Pulse Mode

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Cortex ® -M0+ MCU

In the Single Pulse mode, the STI active edge which sets the TME bit to 1 will enable the counter.

However, there exist several clock delays to perform the comparison result between the counter value and the CHxCR value. In order to reduce the delay to a minimum value, the user can set the

CHxIMAE bit in each CHxOCFR register. After a STI rising edge trigger occurs in the single pulse mode, the CHxOREF signal will immediately be forced to the state which the CHxOREF signal will change to as the compare match event occurs without taking the comparison result into account. The CHxIMAE bit is available only when the output channel is configured to operate in the PWM mode 1 or PWM mode 2 and the trigger source is derived from the STI signal.

Counter Value

Up-Counting Mode

CRR 6

5

CHxCR 4

3

2

1

0

Time

GT_CNT

ITIx

STI

TME

Counter Start Time

CHxIMAE

CHxOREF

(PWM1)

(PWM2)

Minimum delay

Figure 168. Immediate Active Mode Minimum Delay

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Asymmetric PWM Mode

Asymmetric PWM mode allows two center-aligned PWM signals to be generated with a programmable phase shift. While the PWM frequency is determined by the value of the CRR register, the duty cycle and the phase-shift are determined by the CHxCR and CHxACR register.

When the counter is counting up, the PWM uses the value in CHxCR as up-count compare value.

When the counter is into counting down stage, the PWM uses the value in CHxACR as downcount compare value. The Figure 169 is shown an example for asymmetric PWM mode in centeraligned counting mode.

Note: Asymmetric PWM mode can only be operated in center-aligned counting mode.

CNTR 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1

CRR = 8


CRR = 8

CR = 3, ACR = X

CR = 3

CHxOREF


CRR = 8

CR = 5, ACR = X

CR = 5

CHxOREF


CRR = 8

CR = 3, ACR = 5

CR = 3

ACR = 5

CHxOREF


CRR = 8

CR = 5, ACR = 3

CR = 5

ACR = 3

CHxOREF

Figure 169. Asymmetric PWM Mode versus Center-aligned Counting Mode

Phase delay = 2

Timer Interconnection

The timers can be internally connected together for timer chaining or synchronization. This can be implemented by configuring one timer to operate in the Master mode while configuring another timer to be in the Slave mode. The following figures present several examples of trigger selection for the master and slave modes.

Using one timer to enable/disable another timer start or stop counting

▆

Configure PWM0 as the master mode to send its channel 0 Output Reference signal CH0OREF as a trigger output (MMSEL = 0x4).

▆

▆

Configure PWM0 CH0OREF waveform.

Configure PWM1 to receive its input trigger source from the PWM0 trigger output (TRSEL =

0x9).

▆

▆

▆

Configure PWM1 to operate in the pause mode (SMSEL = 0x5).



Rev. 1.00 487 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Master PWM0 f

CLKIN

PWM0

CH0OREF

PWM0

CNTR

32

Slave PWM1

PWM1

CNTR

PWM1

TEVIF

33

FA

34

FB

35

Figure 170. Pausing PWM1 using the PWM0 CH0OREF Signal

FC

36

Software clearing

00

FD

01

Using one timer to trigger another timer start counting

▆

Configure PWM0 to operate in the master mode to send its Update Event UEV as the trigger output (MMSEL = 0x2).

▆

▆

▆

Configure the PWM0 period by setting the CRR register.

Configure PWM1 to get the input trigger source from the PWM0 trigger output (TRSEL = 0x9).


▆

Start PWM0 by writing ‘1’ to the TME bit.

f

CLKIN

PWM0

UEVIF

PWM0

CNTR 13 14 15 00

PWM1

CNTR

PWM1

TME bit

PWM1

TEVIF

FA FB

Software clearing

Figure 171. Triggering PWM1 with PWM0 Update Event

01

FC

02

FD

03

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32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Starting two timers synchronously with the master enable MTO signal trigger

▆

Configure PWM0 to operate in the master mode to send its enable signal as a trigger output

(MMSEL = 0x1).

▆

▆

▆

▆

Enable the PWM0 master timer synchronization function by setting the TSE bit in the MDCFR register to 1 to synchronize the slave timer.

Configure PWM1 to receive its input trigger source from the PWM0 trigger output (TRSEL = 0x9).


Start PWM0 by writing ‘1’ to the TME bit.

Master PWM0 f

DTS

=f

CLKIN

PWM0 (TME bit)

PWM0 CK_PSC

TSE=1

Delay

PWM0 CNTR 34

Write UEVG bit

0 1 2 3

ITI

Slave PWM1

PWM1 (TME bit)

PWM1 (TEVIF)

PWM1 CK_PSC

PWM1 CNTR 11 0

Write UEVG bit

1 2

Figure 172. Trigger PWM0 and PWM1 with the PWM0 Timer Enable Signal

3

4 5

4 5

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32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Trigger Peripherals Start

To interconnect to the peripherals, such as ADC, Timer and so on, the PWM could output the MTO signal or the channel compare match output signal CHxOREF (x = 0 ~ 3) to be used as peripherals input trigger signal and depending on the MCU specification.

PDMA Request

The PWM supports the interface for PDMA data transfer. There are certain events which can generate the PDMA requests if the corresponding enable control bits are set to 1 to enable the

PDMA access. These events are the PWM update events, trigger events and channel compare events. When the PDMA request is generated from the PWM channel, it can be derived from the channel compare event or the PWM update event selected by the channel PDMA selection bit, CHCDS, for all channels. For more detailed PDMA configuring information, refer to the corresponding section in the PDMA chapter.

CHCDS

CH0CDE

CH0_EV

UEV_EV

CH1_EV

UEV_EV

CH2_EV

UEV_EV

CH3_EV

UEV_EV

UEV_EV

UEVDE

0

1

0

1

0

1

0

1

CH1CDE

CH2CDE

CH3CDE

CH0 PDMA Request

CH1 PDMA Request

CH2 PDMA Request

CH3 PDMA Request

UEV PDMA Request

TRIG_EV

TEVDE

Figure 173. PWM PDMA Mapping Diagram

Trigger PDMA Request

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32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Register Map

The following table shows the PWM registers and reset values.

Table 64. PWM Register Map

Register

CNTCFR

MDCFR

TRCFR





CTR

CH0OCFR

CH1OCFR

CH2OCFR

CH3OCFR

CHCTR

CHPOLR

DICTR

EVGR

INTSR

CNTR

PSCR

CRR

CH0CR

CH1CR

CH2CR

CH3CR

CH0ACR

CH1ACR

CH2ACR

CH3ACR





0x04C Channel 3 Output Configuration Register



0x074 Timer PDMA / Interrupt Control Register





0x088 Timer Counter-Reload Register

0x090 Channel 0 Compare Register



0x09C Channel 3 Compare Register




0x0AC Channel 3 Asymmetric Compare Register

Reset Value

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_FFFF

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

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32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU



This register specifies the PWM counter configuration.

Offset: 0x000


31 30 29

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

21

13

5

28

Reserved

20

Reserved

27

19

12

4

Reserved

11

Reserved

3

Type/Reset

26

18

10

2

Bits

[24]

[17:16]

[1]

Field

DIR

CMSEL

UGDIS

25 24

DIR

RW 0

17 16

CMSEL

RW 0 RW 0

9 8

1

UGDIS

0

UEVDIS

RW 0 RW 0

Descriptions

Counting Direction

0: Count-up

1: Count-down

Note: This bit is read only when the Timer is configured to be in the Center-aligned mode.

Counter Mode Selection

00: Edge-aligned mode. Normal up-counting and down-counting available for this mode. Counting direction is defined by the DIR bit.

01: Center-aligned mode 1. The counter counts up and down alternatively. The compare match interrupt flag is set during the count-down period.

10: Center-aligned mode 2. The counter counts up and down alternatively. The compare match interrupt flag is set during the count-up period.

11: Center-aligned mode 3. The counter counts up and down alternatively. The compare match interrupt flag is set during the count-up and count-down periods.


0: Any of the following events will generate an update PDMA request or interrupt




1: Only counter overflow/underflow generates an update PDMA request or interrupt

Rev. 1.00 492 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Bits

[0]

Field

UEVDIS

Descriptions

Update event Disable control







This register specifies the PWM master and slave mode selection and single pulse mode.

Offset: 0x004


Type/Reset

Type/Reset

Type/Reset

Type/Reset

31

23

15

7

30

22

14

6

29

21

Reserved

28

Reserved

20

13

Reserved

5

12

4

Reserved

27

19

11

3

26 25 24

SPMSET

RW 0

16 18 17

MMSEL

RW 0 RW 0 RW 0

10 9 8

SMSEL

RW 0 RW 0 RW 0

2 1 0

TSE

RW 0

Bits

[24]

Field

SPMSET

Descriptions

Single Pulse Mode Setting

0: Counter counts normally irrespective of whether the update event occurred or not.

1: Counter stops counting at the next update event and then the TME bit is cleared by hardware.

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HT32F5828

Cortex ® -M0+ MCU

Bits

[18:16]

Field

MMSEL

Descriptions

Master Mode Selection

Master mode selection is used to select the MTO signal source which is used to synchronize the other slave timer.

MMSEL [2:0] Mode

000

001

010

011

Reset Mode

Enable Mode

Update Mode

—

Descriptions

The MTO signal in the Reset mode is an output derived from one of the following cases:

1. Software setting UEVG bit

2. The STI trigger input signal which will be output on the MTO signal line when the Timer is used in the slave Restart mode

The Counter Enable signal is used as the trigger output.

The update event is used as the trigger output according to one of the following cases when the

UEVDIS bit is cleared to 0:

1. Counter overflow / underflow

2. Software setting UEVG

3. Slave trigger input when used in slave restart mode

Reserved

100

101

110

111

Rev. 1.00 494 of 637 December 28, 2020

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HT32F5828

Cortex ® -M0+ MCU

Bits

[11:8]

[0]

Field

SMSEL

TSE

Descriptions


SMSEL [2:0]

000

001

010

011

100

101

110

111

Mode Descriptions

Disable mode The prescaler is clocked directly by the internal clock.

— Reserved

—

—

Restart Mode

Reserved

Reserved

The counter value restarts from 0 or the CRR shadow register value depending upon the counter mode on the rising edge of the STI signal. The registers will also be updated.

Pause Mode

Trigger Mode

STIED

The counter starts to count when the selected trigger input STI is high. The counter stops counting on the instant, not being reset, when the STI signal changes its state to a low level. Both the counter start and stop control are determined by the STI signal.



Timer Synchronization Enable

0: No action

1: Master timer (current timer) will generate a delay to synchronize its slave timer through the MTO signal.

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Cortex ® -M0+ MCU


This register specifies the trigger source selection of PWM.

Offset: 0x008


31 30 29 28

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

21

13

5

Reserved

20

12

4

27

Reserved

19

Reserved

26

18

25

17

24

16

11

Reserved

10 9 8

3 2 1

TRSEL

0

RW 0 RW 0 RW 0 RW 0

Bits

[3:0]

Field

TRSEL

Descriptions







Others: Reserved


Table 65. PWM Internal Trigger Connection

Slave Timing Module

PWM0

PWM1

ITI0

PWM1

PWM0

ITI1

GPTM

GPTM

ITI2

—

—

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Cortex ® -M0+ MCU


This register specifies the timer enable bit (TME), CRR buffer enable bit (CRBE) and Channel PDMA selection bit (CHCDS).

Offset: 0x010


31 30 29 26 25 24

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

21

13

5

28

20

Reserved

27

Reserved

19

12

4

Reserved

11

Reserved

3

18

10

2

17

9

16

CHCDS

RW 0

8

1

CRBE

0

TME

RW 0 RW 0

Bits

[16]

[1]

[0]

Field

CHCDS

CRBE

TME

Descriptions

Channel PDMA event selection

0: Channel PDMA request derived from the channel compare event.

1: Channel PDMA request derived from the Update event.


0: Counter-reload register can be updated immediately

1: Counter-reload register can not be updated until the update event occurs

Timer Enable bit

0: PWM off

1: PWM on

When the TME bit is cleared to 0, the counter is stopped and the PWM consumes no power in any operation mode except for the single pulse mode and the slave trigger mode. In these two modes the TME bit can automatically be set to 1 by hardware which permits all the PWM registers to function normally.

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Cortex ® -M0+ MCU



Offset: 0x040


31

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

30

22

29

21

28

20

27

Reserved

19

Reserved

26

18

25

17

24

16

14 13 12 11

Reserved

6 5 4 3


RW 0 RW 0

10

2

9

1

CH0OM[2:0]

8

CH0OM[3]

RW 0

0

RW 0 RW 0 RW 0

Bits

[5]

[4]



0: No action


The CH0OREF signal will be forced to the compare matched level immediately after an available trigger event occurs irrespective of the result of the comparison between the CNTR and the CH0CR values.



CH0PRE Channel 0 Compare Register (CH0CR) Preload Enable

0: CH0CR preload function is disabled

The CH0CR register can be immediately assigned a new value when the

CH0PRE bit is cleared to 0 and the updated CH0CR value is used immediately.

1: CH0CR preload function is enabled

The new CH0CR value will not be transferred to its shadow register until the update event occurs.

Rev. 1.00 498 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Bits

[8][2:0]




0000: No Change






0110: PWM mode 1

- During up-counting, channel 0 has an active level when CNTR < CH0CR or otherwise has an inactive level.


CH0CR or otherwise has an active level.

0111: PWM mode 2

- During up-counting, channel 0 is has an inactive level when CNTR <



CH0CR or otherwise has an inactive level.









CH0ACR or otherwise has an inactive level.


Selection bit in Counter Configuration Register must be configured as Centeraligned Counting mode (CMSEL = 0x1/0x2/0x3)

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Cortex ® -M0+ MCU



Offset: 0x044


31

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

30

22

29

21

28

20

27

Reserved

19

Reserved

26

18

25

17

24

16

14 13 12 11

Reserved

6 5 4 3


RW 0 RW 0

10

2

9

1

CH1OM[2:0]

8

CH1OM[3]

RW 0

0

RW 0 RW 0 RW 0

Bits

[5]

[4]



0: No action






0: CH1CR preload function is disabled.

The CH1CR register can be immediately assigned a new value when the CH1PRE bit is cleared to 0 and the updated CH1CR value is used immediately.



Rev. 1.00 500 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Bits

[8][2:0]




0000: No Change






0110: PWM mode 1




0111: PWM mode 2
















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Cortex ® -M0+ MCU



Offset: 0x048


31

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

30

22

29

21

28

20

27

Reserved

19

Reserved

26

18

25

17

24

16

14 13 12 11

Reserved

6 5 4 3


RW 0 RW 0

10

2

9

1

CH2OM[2:0]

8

CH2OM[3]

RW 0

0

RW 0 RW 0 RW 0

Bits

[5]

[4]



0: No action











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HT32F5828

Cortex ® -M0+ MCU

Bits

[8][2:0]




0000: No Change






0110: PWM mode 1




0111: PWM mode 2
















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HT32F5828

Cortex ® -M0+ MCU



Offset: 0x04C


31

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

30

22

29

21

28

20

27

Reserved

19

Reserved

26

18

25

17

24

16

14 13 12 11

Reserved

6 5 4 3


RW 0 RW 0

10

2

9

1

CH3OM[2:0]

8

CH3OM[3]

RW 0

0

RW 0 RW 0 RW 0

Bits

[5]

[4]



0: No action











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HT32F5828

Cortex ® -M0+ MCU

Bits

[8][2:0]




0000: No Change






0110: PWM mode 1




0111: PWM mode 2




CH3CR or otherwise has an inactive level












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HT32F5828

Cortex ® -M0+ MCU


This register contains the channel compare output function enable control bits.

Offset: 0x050


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

Type/Reset

Type/Reset

15 14 13 12 11

Reserved

10 9 8

7

Reserved

6

CH3E

RW 0

5

Reserved

4

CH2E

RW 0

3

Reserved

2

CH1E

RW 0

1

Reserved

0

CH0E

RW 0

Bits

[6]

[4]

[2]

[0]

Field

CH3E

CH2E

CH1E

CH0E

Descriptions

Channel 3 Compare Enable












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HT32F5828

Cortex ® -M0+ MCU


This register contains the channel compare output polarity control.

Offset: 0x054


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

Type/Reset

Type/Reset

15 14 13 12 11

Reserved

10 9 8

7

Reserved

6

CH3P

RW 0

5

Reserved

4

CH2P

RW 0

3

Reserved

2

CH1P

RW 0

1

Reserved

0

CH0P

RW 0

Bits

[6]

[4]

[2]

[0]

Field

CH3P

CH2P

CH1P

CH0P

Descriptions

Channel 3 Compare Polarity












Rev. 1.00 507 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Timer PDMA/Interrupt Control Register – DICTR

This register contains the timer PDMA and interrupt enable control bits.

Offset: 0x074


Type/Reset

Type/Reset

Type/Reset

Type/Reset

31

23

15

7

30

22

14

6

29

Reserved

21

Reserved

13

Reserved

5

Reserved

28

20

12

4

27 26 25 24

TEVDE Reserved UEVDE

RW 0 RW 0

19 18 17 16

CH3CDE CH2CDE CH1CDE CH0CDE

RW 0 RW 0 RW 0 RW 0

11 10

TEVIE

9

Reserved

8

UEVIE

3

CH3CIE

RW 0

2 1

CH2CIE CH1CIE

RW 0

0

CH0CIE

RW 0 RW 0 RW 0 RW 0

Bits

[26]

[24]

[19]

[18]

[17]

[16]

[10]

[8]

[3]

[2]

Field

TEVDE

UEVDE

CH3CDE

CH2CDE

CH1CDE

CH0CDE

TEVIE

UEVIE

CH3CIE

CH2CIE

Descriptions

Trigger event PDMA Request Enable

0: Trigger PDMA request is disabled

1: Trigger PDMA request is enabled

Update event PDMA Request Enable

0: Update event PDMA request is disabled

1: Update event PDMA request is enabled

Channel 3 Compare PDMA Request Enable












Trigger event Interrupt Enable






Channel 3 Compare Interrupt Enable






Rev. 1.00 508 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Bits

[1]

[0]

Field

CH1CIE

CH0CIE

Descriptions









Offset: 0x078


31 30 29 28

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

21

13

Reserved

5

Reserved

20

12

4

27

Reserved

19

Reserved

26

18

25

17

24

16

11 10

TEVG

9

Reserved

8

UEVG

3

CH3CG

WO 0

2

CH2CG

1

CH1CG

WO 0

0

CH0CG

WO 0 WO 0 WO 0 WO 0

Bits

[10]

[8]

[3]

Field

TEVG

UEVG

CH3CG

Descriptions



0: No action




0: No action


The counter value returns to 0 or the CRR preload value, depending on the counter mode in which the current timer is being used. An update operation of any related registers will also be performed. For more detailed descriptions, refer to the corresponding section.

Channel 3 Compare Generation

A Channel 3 compare event can be generated by software setting this bit. It is cleared by hardware automatically.

0: No action

1: Compare event is generated on channel 3

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HT32F5828

Cortex ® -M0+ MCU

Bits

[2]

[1]

[0]

Field

CH2CG

CH1CG

CH0CG

Descriptions



0: No action




0: No action




0: No action




Offset: 0x07C


31 30 29 28

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

21

13

Reserved

5

Reserved

20

12

4

27

Reserved

19

Reserved

26

18

25

17

24

16

11 10

TEVIF

9

Reserved

8

UEVIF

W0C 0 W0C 0

3

CH3CIF

2

CH2CIF

1

CH1CIF

0

CH0CIF

W0C 0 W0C 0 W0C 0 W0C 0

Bits

[10]

Field

TEVIF

Descriptions





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Cortex ® -M0+ MCU

Bits

[8]

[3]

[2]

[1]

[0]

Field

UEVIF

CH3CIF

CH2CIF

CH1CIF

CH0CIF

Descriptions






- The counter overflows or underflows



Channel 3 Compare Interrupt Flag


1: The content of the counter CNTR has matched the contents of the CH3CR register.

This flag is set by hardware when the counter value matches the CH3CR value except in the center-aligned mode. It is cleared by software.



1: The content of the counter CNTR has matched the contents of the CH2CR register




1: The content of the counter CNTR has matched the contents of the CH1CR register




1: The content of the counter CNTR has matched the content of the CH0CR register


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Cortex ® -M0+ MCU



Offset: 0x080


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

CNTV

10 9 8


7 6 5 4 3 2 1 0

CNTV


Bits

[15:0]

Field

CNTV

Descriptions

Counter Value



Offset: 0x084


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

PSCV

10 9 8


7 6 5 4 3 2 1 0

PSCV


Bits

[15:0]

Field

PSCV

Descriptions

Prescaler Value


CK_CNT

.

f

CK_CNT

= f

CK_PSC

PSCV[15:0]+1

, where the f

CK_PSC


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Cortex ® -M0+ MCU

Timer Counter-Reload Register – CRR

This register specifies the timer counter-reload value.

Offset: 0x088


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

CRV

10 9 8


7 6 5 4 3 2 1 0

CRV


Bits

[15:0]

Field

CRV

Descriptions

Counter-Reload Value


Channel 0 Compare Register – CH0CR

This register specifies the timer channel 0 compare value.

Offset: 0x090


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

CH0CV

10 9 8


7 6 5 4 3 2 1 0

CH0CV


Bits

[15:0]

Field

CH0CV

Descriptions

Channel 0 Compare Value

The CH0CR value is compared with the counter value and the comparison result is used to trigger the CH0OREF output signal.

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Cortex ® -M0+ MCU



Offset: 0x094


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

CH1CV

10 9 8


7 6 5 4 3 2 1 0

CH1CV


Bits

[15:0]

Field

CH1CV

Descriptions





Offset: 0x098


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

CH2CV

10 9 8


7 6 5 4 3

CH2CV

2 1 0


Bits

[15:0]

Field

CH2CV

Descriptions



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HT32F5828

Cortex ® -M0+ MCU



Offset: 0x09C


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

CH3CV

10 9 8


7 6 5 4 3 2 1 0

CH3CV


Bits

[15:0]

Field

CH3CV

Descriptions





Offset: 0x0A0


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

CH0ACV

10 9 8


7 6 5 4 3

CH0ACV

2 1 0


Bits

[15:0]

Field

CH0ACV

Descriptions



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Offset: 0x0A4


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

CH1ACV

10 9 8


7 6 5 4 3 2 1 0

CH1ACV


Bits

[15:0]

Field

CH1ACV

Descriptions





Offset: 0x0A8


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

CH2ACV

10 9 8


7 6 5 4 3

CH2ACV

2 1 0


Bits

[15:0]

Field

CH2ACV

Descriptions



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HT32F5828

Cortex ® -M0+ MCU



Offset: 0x0AC


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

CH3ACV

10 9 8


7 6 5 4 3 2 1 0

CH3ACV


Bits

[15:0]

Field

CH3ACV

Descriptions



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24

Single-Channel Timer (SCTM)

Introduction

The Single-Channel Timer consists of one 16-bit up-counter, one 16-bit Capture/Compare Register

(CCR), one 16-bit Counter-Reload Register (CRR) and several control/status registers. It can be used for a variety of purposes including general timer, input signal pulse width measurement or output waveform generation such as PWM output. f

CLKIN

TIBED

TISED

STIED

Clock

Controller

UEVG

TIS

Trigger

Controller

MDCFR

Register

STI Slave

Controller

TEV

TEV : Trigger Event

CEV : Capture Event

MEV : Compare Match Event

UEV : Update Event

SCTM_CH

TI Input Filter


& Edge Detection

TISED

TIBED

CK_PSC PSC

PRESCALER

CK_CNT

Restart

Pause

Trigger

TM_CNT

Reload

Register

(CRR)

UEV

CH

PRESCALER

CEV

Channel Capture/Compare

Register (CHCCR)

MEV

CHOREF Output

Control

Figure 174. SCTM Block Diagram

SCTM_CHO

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Cortex ® -M0+ MCU

Features

▆

▆

▆

▆

16-bit auto-reload up-counter

16-bit programmable prescaler that allows division of the counter clock frequency by any factor between 1 and 65536

Single channel for:

● Input Capture function


● PWM waveform output

Interrupt generation with the following events:

● Update event

●

● Input capture event

●

Trigger event

Output compare match event


Counter Mode

Up-Counting

The counter counts continuously from 0 to the counter-reload value, which is defined in the

CRR register. Once the counter reaches the counter-reload value, the Timer Module generates an overflow event and the counter restarts to count once again from 0. This action will continue repeatedly. When the update event is generated by setting the UEVG bit in the EVGR register to 1, the counter value will also be initialized to 0.

CK_PSC

CNT_EN

CK_CNT

CNTR

CRR

CRR Shadow Register

PSCR

PSCR Shadow Register

PSC_CNT

Counter Overflow

Update Event Flag

F5

F2

0

F5

Write a new value


0

0

F3 F4 F5

0

0


1

36

0

1

1

1

36

1

0

2

1

Software clearing

0

3

1

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▆


CLKIN


0x6, the internal APB clock f

CLKIN

CLKIN

used to drive the counter prescaler when the slave mode is disabled. When the slave mode selection bits SMSEL are set to 0x4, 0x5 or

is the counter prescaler driving clock source. If the slave mode controller is enabled by setting SMSEL field in the MDCFR register to 0x7, the prescaler is clocked by other clock sources selected by the TRSEL field in the TRCFR register and described as follows.

▆

STIED




PSCR CRR

Update Event f

CLKIN

(Internal APB clock)

STIED

(Trigger events)

CK_PSC

CLK

PSC Prescaler

Reset

CK_CNT

CLK

CNTR

Reset

TM_CNT

TRSEL

SMSEL

Start/Stop

Figure 176. SCTM Clock Source Selection

Overflow

UEVG bit


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Cortex ® -M0+ MCU


The trigger controller is used to select the trigger source and setup the trigger level or edge trigger condition. For the internal trigger input, it can be selected by the Trigger Selection bits TRSEL in the TRCFR register. For all the trigger sources except the UEVG bit software trigger, the internal edge detection circuitry will generate a clock pulse at each trigger signal rising edge to stimulate some SCTM functions which are triggered by a trigger signal rising edge.

Edge Trigger Source = Channel input


0

TISED

TIBED

Reserved

Reserved

Reserved

Reserved

000

001

010

011 others

Reserved

Reserved

Reserved

TRSEL[2:0]

STIED_S1

000

001

010

011 others STIED_S0

0

1

TRSEL[3]

STIED

Level Trigger Source = Channel input + Software UEVG bit

S/W Set

UEVG Bit

TIS


TRSEL[2:0]

Reserved

Reserved

Reserved

0

Reserved

Reserved

Reserved

Reserved

000

001

010

011 others

STI_S1

000

001

010

011 others

STI_S0

0

1

TRSEL[3]


STI

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Cortex ® -M0+ MCU


The SCTM can be synchronized with an external trigger in several modes including the Restart mode, the Pause mode and the Trigger mode which is selected by the SMSEL field in the MDCFR register. The trigger input of these modes comes from the STI signal which is selected by the

TRSEL field in the TRCFR register. The operation modes in the Slave Controller are described in the accompanying sections.

Trigger Controller

STI

Slave

Controller

SMSEL

Trigger Event


Restart/Pause/Trigger Mode


Restart Mode




STI source signal

(polarity=0)

STI source signal

(polarity=1)

STI

CK_CNT

UEVG bit

(reset counter)

CNTR

(Up-counting)

TEVIF

27 28 29

Figure 179. SCTM in Restart Mode

Sync.

30 31

Trigger Event

0 1 2

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Cortex ® -M0+ MCU

Pause Mode

In the Pause Mode, the selected STI input signal level is used to control the counter start/stop operation. The counter starts to count when the selected STI signal is at a high level and stops counting when the STI signal is changed to a low level, here the counter will maintain its present value and will not be reset. Since the Pause function depends upon the STI level to control the counter stop/start operation, the selected STI trigger signal can not be derived from the TIBED signal.

STI source signal

(polarity=0)

STI source signal

(polarity=1)

STI

CK_ CNT

CNT_ EN

CNTR

TEVIF

Sync

27 28 29

Sync

30 31

Software clearing

Figure 180. SCTM in Pause Mode

Trigger Mode


STI source signal

(polarity=0)

STI source signal

(polarity=1)

STI

CK_CNT

CNT_EN

CNTR

(Up-counting)

TEVIF

27

Sync

28 29 30 31 32

Software clearing

Figure 181. SCTM in Trigger Mode

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Cortex ® -M0+ MCU


The SCTM channel can be used as the capture input or compare match output. The capture input or compare match output channel is composed of a preload register and a shadow register. Data access of the APB bus is always implemented by reading/writing the preload register.

When used in the input capture mode, the counter value is captured into the CHCCR shadow register first and then transferred into the CHCCR preload register when the capture event occurs.

When used in the compare match output mode, the contents of the CHCCR preload register is copied into the associated shadow register; the counter value is then compared with the register value.

APB Bus Interface

CHPSC

Read CHCCR

Capture

Controller

CHCCS

CHCCG

CHE

Capture Transfer

CHCCR

(Preload Register)

Compare Transfer

Compare

Controller

CHCCR

(Shadow Register)

Capture

CHCCS

CHPRE

CHCCR

TM_CNT

Figure 182. Capture/Compare Block Diagram

Write CHCCR

Update Event

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Cortex ® -M0+ MCU

Capture Counter Value Transferred to CHCCR

When the channel is used as a capture input, the counter value is captured into the Channel

Capture/Compare Register (CHCCR) when an effective input signal transition occurs. Once the capture event occurs, the CHCCIF flag in the INTSR register is set accordingly. If the CHCCIF bit is already set, i.e., the flag has not yet been cleared by software, and another capture event on this channel occurs, the corresponding channel Over-Capture flag, named CHOCF, will be set.

f

CLKIN

SCTM_CH

CNTR 25

CHCCR 0

26

CHCCIF

CHOCF

Figure 183. Input Capture Mode

27 28

26

29 30 31 32 33 34 35

32

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Cortex ® -M0+ MCU

Input Stage

The input stage consists of a digital filter, a channel polarity selection, edge detection and a channel prescaler. The channel input signal (TI) is sampled by a digital filter to generate a filtered input signal TIFP. Then the channel polarity and the edge detection block can generate a TISED signal for the input capture function. The effective input event number can be set by the channel capture input source prescaler setting field (CHPSC).

f

CLKIN

Edge

Detection

Edge

Detection

CHCCS

TIBED

SCTM_CH

TI f sampling

Filter

TIFP TIFN

TIF

Figure 184. Channel Input Stages f

CLKIN

TIS

CHP

Edge

Detection

TISED

CH

PRESCALER

CHPSC

CHPSC

CHCAP Event

Digital Filter

The digital filter is embedded in the channel input stage. The digital filter in the SCTM is an N-event counter where N refers to how many valid transitions are necessary to output a filtered signal. The

N value can be 0, 2, 4, 5, 6 or 8 according to the user selection for this digital filter.

No Filtered

Digital Filter (N=2)

TI

D Q D Q D Q f

SYSTEM

CK CK f sampling

CK

Figure 185. TI Digital Filter Diagram with N = 2

J

CK

Q

K

Filtered

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Cortex ® -M0+ MCU

Output Stage

The SCTM output has function for compare match or PWM output. The channel output SCTM_

CHO is controlled by the CHOM, CHP and CHE bits in the corresponding CHOCFR, CHPOLR and CHCTR registers.

CNTR

CHCCR f

CLKIN

Output Mode

Controller

CHOREF

CHP

CHOM


Output Enable

Controller

CHE

SCTM_CHO

CHOREF

CHCMP Event


When the SCTM is used in the compare match output mode, the CHOREF signal (Channel Output

Reference signal) is defined by the CHOM bit setup. The CHOREF signal has several types of output function which defines what happens to the output when the counter value matches the contents of the CHCCR register. In addition to the low, high and toggle CHOREF output types; there are also PWM mode 1 and PWM mode 2 outputs. In these modes, the CHOREF signal level is changed according to the relationship between the counter value and the CHCCR content. There are also two modes which will force the output into an inactive or active state irrespective of the

CHCCR content or counter values. With regard to a more detailed description refer to the relative bit definition. The Table 66 shows a summary of the output type setup.


CHOM value

0x0

0x1

No change

Clear Output to 0


0x2

0x3

0x4

0x5

0x6

0x7

Set Output to 1

Toggle Output


Force Active Level

PWM Mode 1

PWM Mode 2

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Cortex ® -M0+ MCU

Counter Value

CRR

CHCCR

(New value 2)

CHCCR

(New value 3)

CHCCR

(New value 1)

CHCCR

Update

CHCCR value

TME

CHOREF

CHOM=0x3, CHPRE=0


(1) (2) (3)

Time

Figure 187. Toggle Mode Channel Output Reference Signal (CHPRE = 0)

Counter Value

CRR

CHCCR

(New value 2)

CHCCR

(New value 3)

CHCCR

(New value 1)

CHCCR

Update

CHCCR value

TME

CHOREF

CHOM=0x3, CHPRE=1


(1) (2) (3)

Figure 188. Toggle Mode Channel Output Reference Signal (CHPRE = 1)

Time

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Cortex ® -M0+ MCU

Counter Value

CRR

CHCCR

Counter Value

CHCCR

CRR

CHOM = 0x6

100%

CHOREF

CHCCIF

CHOREF

CHCCIF

CHOM = 0x7

CHOREF

Figure 189. PWM Mode Channel Output Reference Signal

Counter Value

CRR

CHCCR = 0x0000

CHOREF

CHCCIF

0%


The Update event is used to update the CRR, the PSCR and the CHCCR values from the actual registers to the corresponding shadow registers. An update event will occur when the counter overflows, the software update control bit is triggered or an update event from the slave controller is generated.


UEVDIS and UGDIS bit definition in the CNTCFR register.

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Counter Overflow

UEVG

Slave Restart mode

UEVDIS


Counter Overflow

UEVG

Slave Restart mode

UEVDIS

UGDIS


Register Map

The following table shows the SCTM registers and reset values.

Table 67. SCTM Register Map

Register

CNTCFR



MDCFR

TRCFR

CTR

CHICFR

CHOCFR

CHCTR

CHPOLR

DICTR

EVGR

INTSR

CNTR

PSCR

CRR

CHCCR




0x020 Channel Input Configuration Register

0x040 Channel Output Configuration Register



0x074 Timer Interrupt Control Register





0x088 Timer Counter Reload Register

0x090 Channel Capture/Compare Register


CHCCR Shadow Registers)

UEV interrupt

Reset Value

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_FFFF

0x0000_0000

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This register specifies the SCTM counter configuration.

Offset: 0x000


31 30 29

Type/Reset

Type/Reset

Type/Reset

Type/Reset

Bits

[9:8]

[1]

[0]

23

15

7

Field

CKDIV

UGDIS

UEVDIS

22

14

6

21

13

5

28

20

12

Reserved

4

Reserved

27

Reserved

19

Reserved

11

3

26

18

10

2

25

17

24

16

9 8

CKDIV

RW 0 RW 0

1 0

UGDIS UEVDIS

RW 0 RW 0

Descriptions

Clock Division

These two bits define the frequency ratio between the timer clock (f dead-time clock (f clock.

00: f

01: f

10: f

DTS

= f

DTS

= f

DTS

= f

CLKIN

CLKIN

/ 2

CLKIN

/ 4

11: Reserved

CLKIN

) and the

DTS

). The dead-time clock is also used for digital filter sampling


0: Any of the following events will generate an update interrupt

- Counter overflow



1: Only counter overflow generates an update interrupt

Update event Disable control


- Counter overflow




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Cortex ® -M0+ MCU


This register specifies the SCTM slave mode selection.

Offset: 0x004


31 30 29 28

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

21

13

Reserved

5

20

12

4

27

Reserved

19

Reserved

26

18

25

17

24

16

11

3

Reserved

10 9

SMSEL

8

RW 0 RW 0 RW 0

2 1 0

Type/Reset

Bits

[10:8]

Field

SMSEL

Descriptions


SMSEL [2:0]

000

Mode Descriptions

Disable mode The prescaler is clocked directly by the internal clock.

100

101

110

111

Others

Pause Mode

Trigger Mode

STIED

The counter starts to count when the selected trigger input STI is high. The counter stops counting on the instant, not being reset, when the STI signal changes its state to a low level. Both the counter start and stop control are determined by the STI signal.



Reserved

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Cortex ® -M0+ MCU


This register specifies the trigger source selection of SCTM.

Offset: 0x008


31 30 29 28

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

21

13

5

Reserved

20

12

4

27

Reserved

19

Reserved

26

18

25

17

24

16

11

Reserved

10 9 8

3 2 1

TRSEL

0

RW 0 RW 0 RW 0 RW 0

Bits

[3:0]

Field

TRSEL

Descriptions




0001: Filtered input of the channel (TIS)

1000: Channel both edge detector (TIBED)

Others: Reserved


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Cortex ® -M0+ MCU


This register specifies the timer enable bit (TME), CRR buffer enable bit (CRBE).

Offset: 0x010


31 30 29

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

21

13

5

28

20

27

Reserved

19

Reserved

12

4

Reserved

11

Reserved

3

Type/Reset

26

18

10

2

Bits

[1]

[0]

Field

CRBE

TME

25

17

9

24

16

8

1

CRBE

0

TME

RW 0 RW 0

Descriptions


0: Counter reload register can be updated immediately

1: Counter reload register cannot be updated until the update event occurs

Timer Enable bit

0: SCTM off

1: SCTM on – SCTM functions normally

When the TME bit is cleared to 0, the counter is stopped and the SCTM consumes no power in any operation mode except for the slave trigger mode. In this mode the TME bit can automatically be set to 1 by hardware which permits all the SCTM registers to function normally.

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HT32F5828

Cortex ® -M0+ MCU

Channel Input Configuration Register – CHICFR

This register specifies the channel input mode configuration.

Offset: 0x020


31 30 29 28

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

21

Reserved

13

5

Reserved

20

12

4

27

Reserved

26 25 24

19 18

CHPSC

17 16

CHCCS

RW 0 RW 0 RW 0 RW 0

11

Reserved

10 9 8

3 2 1

TIF

0

RW 0 RW 0 RW 0 RW 0

Bits

[19:18]

[17:16]

Field

CHPSC

CHCCS

Descriptions

Channel Capture Input Source Prescaler Setting

These bits define the effective events of the channel capture input. Note that the prescaler is reset once the Channel Capture/Compare Enable bit, CHE, in the


00: No prescaler, channel capture input signal is chosen for each active event.

01: Channel Capture input signal is chosen for every 2 events.



Channel Capture/Compare Selection.

00: Channel is configured as an output.

01: Channel is configured as an input derived from the TI signal.

10: Reserved.

11: Channel is configured as an input which comes from the TIBED signal.

Note: The CHCCS field can be accessed only when the CHE bit is cleared to 0.

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HT32F5828

Cortex ® -M0+ MCU

Bits

[3:0]

Field

TIF

Descriptions

Channel Input Source TI Filter Setting

These bits define the frequency divided ratio used to sample the TI signal. The

Digital filter in the SCTM is an N-event counter where N is defined as how many valid transitions are necessary to output a filtered signal.


SYSTEM

0001: f

0010: f

0011: f

0100: f

0101: f

0110: f sampling sampling

= f

= f sampling

= f sampling

= f

CLKIN

, N = 2

CLKIN

, N = 4

CLKIN

DTS

, N = 8

/ 2, N = 6 sampling

= f

DTS

/ 2, N = 8 sampling

= f

DTS

/ 4, N = 6

.

0111: f

1000: f

1001: f

1010: f

1011: f

1100: f

1101: f

1110: f


= f

= f

= f

= f

DTS

DTS

DTS

DTS

/ 4, N = 8

/ 8, N = 6

/ 8, N = 8

/ 16, N = 5 sampling

= f

DTS


= f

DTS


= f

DTS


= f

DTS


= f

DTS

/ 32, N = 8

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Cortex ® -M0+ MCU

Channel Output Configuration Register – CHOCFR

This register specifies the channel output mode configuration.

Offset: 0x040


31 30 29

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

Reserved

21

13

5

28

20

27

Reserved

19

Reserved

26

18

25

17

24

16

12 11

Reserved

10 9 8

4 3

CHPRE Reserved

RW 0

2 1

CHOM

0

RW 0 RW 0 RW 0

Bits

[4]

[2:0]

Field

CHPRE

CHOM

Descriptions

Channel Capture/Compare Register (CHCCR) Preload Enable

0: CHCCR preload function is disabled

The CHCCR register can be immediately assigned a new value when the

CHPRE bit is cleared to 0 and the updated CHCCR value is used immediately.

1: CHCCR preload function is enabled

The new CHCCR value will not be transferred to its shadow register until the update event occurs.

Channel Output Mode Setting

These bits define the functional types of the output reference signal CHOREF.

000: No Change




100: Force inactive – CHOREF is forced to 0

101: Force active – CHOREF is forced to 1

110: PWM mode 1

- During up-counting, channel has an active level when CNTR < CHCCR or otherwise has an inactive level.

111: PWM mode 2

- During up-counting, channel is has an inactive level when CNTR <

CHCCR or otherwise has an active level.

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Cortex ® -M0+ MCU


This register contains the channel capture input or compare output function enable control bit.

Offset: 0x050


31 30 29 26 25

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

21

13

5

28

20

27

Reserved

19

Reserved

12

4

Reserved

11

Reserved

3

18

10

2

17

9

1

Type/Reset

Bits

[0]

Field

CHE

24

16

8

0

CHE

RW 0

Descriptions

Channel Capture/Compare Enable

- Channel is configured as an input (CHCCS = 0x1/0x3)



- Channel is configured as an output (CHCCS = 0x0)

0: Off – Channel output signal CHO is not active

1: On – Channel output signal CHO generated on the corresponding output pin

Rev. 1.00 538 of 637 December 28, 2020

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HT32F5828

Cortex ® -M0+ MCU


This register contains the channel capture input or compare output polarity control.

Offset: 0x054


31 30 29 26

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

21

13

5

28

20

27

Reserved

19

Reserved

12

4

Reserved

11

Reserved

3

18

10

2

Type/Reset

Bits

[0]

Field

CHP

Descriptions

Channel Capture/Compare Polarity

- When Channel is configured as an input (CHCCS = 0x1/0x3)

0: Capture event occurs on a Channel rising edge

1: Capture event occurs on a Channel falling edge

- When Channel is configured as an output (CHCCS = 0x0)

0: Channel Output is active high

1: Channel Output is active low

25

17

9

1

24

16

8

0

CHP

RW 0

Rev. 1.00 539 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Timer Interrupt Control Register – DICTR

This register contains the timer interrupt enable control bits.

Offset: 0x074


31 30

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

29

21

28

20

13

Reserved

5

12

4

Reserved

27

Reserved

19

Reserved

11

3

26

18

25

17

24

16

10

TEVIE

RW 0

2

9

Reserved

1

8

UEVIE

RW 0

0

CHCCIE

RW 0

Bits

[10]

[8]

[0]

Field

TEVIE

UEVIE

CHCCIE

Descriptions

Trigger event Interrupt Enable






Channel Capture/Compare Interrupt Enable

0: Channel interrupt is disabled

1: Channel interrupt is enabled

Rev. 1.00 540 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU



Offset: 0x078


31 30

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

29

21

28

20

13

Reserved

5

12

4

Reserved

27

Reserved

19

Reserved

11

3

26

18

25

17

24

16

10

TEVG

WO 0

2

9

Reserved

1

8

UEVG

WO 0

0

CHCCG

WO 0

Bits

[10]

[8]

[0]

Field

TEVG

UEVG

CHCCG

Descriptions



0: No action




0: No action


If this bit is set, the counter value returns to 0. An update operation of any related registers will also be performed. For more detail descriptions, refer to the corresponding section.

Channel Capture/Compare Generation

A Channel capture/compare event can be generated by setting this bit. It is cleared by hardware automatically.

0: No action

1: Capture/compare event is generated on channel.

If the channel is configured as an input, the counter value is captured into the

CHCCR register and then the CHCCIF bit is set. If the channel is configured as an output, the CHCCIF bit is set.

Rev. 1.00 541 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU



Offset: 0x07C


31

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

30

22

29

21

28

20

14

6

Reserved

13

Reserved

5

12

4

CHOCF

W0C 0

27

Reserved

19

Reserved

11

3

26

18

25

17

24

16

10

TEVIF

W0C 0

2

Reserved

9

Reserved

1

8

UEVIF

W0C 0

0

CHCCIF

W0C 0

Bits

[10]

[8]

[4]

[0]

Field

TEVIF

UEVIF

CHOCF

CHCCIF

Descriptions










- The counter overflows



Channel Over-Capture Flag



1: Capture event occurs again when the CHCCIF bit is already set and it is not yet cleared by software.

Channel Capture/Compare Interrupt Flag

- Channel is configured as an output:


1: The contents of the counter CNTR have matched the content of the CHCCR register

This flag is set by hardware when the counter value matches the CHCCR value.

It is cleared by software.

- Channel is configured as an input:



This bit is set by hardware on a capture event. It is cleared by software or by reading the CHCCR register.

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HT32F5828

Cortex ® -M0+ MCU



Offset: 0x080


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

CNTV

10 9 8


7 6 5 4 3 2 1 0

CNTV


Bits

[15:0]

Field

CNTV

Descriptions

Counter Value

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32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU



Offset: 0x084


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

PSCV

10 9 8


7 6 5 4 3 2 1 0

PSCV


Bits

[15:0]

Field

PSCV

Descriptions

Prescaler Value


CK_CNT

.

f

CK_CNT

= f

CK_PSC

PSCV[15:0] + 1

, where the f

CK_PSC


Rev. 1.00 544 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Timer Counter Reload Register – CRR

This register specifies the timer counter reload value.

Offset: 0x088


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

CRV

10 9 8


7 6 5 4 3 2 1 0

CRV


Bits

[15:0]

Field

CRV

Descriptions

Counter Reload Value


Rev. 1.00 545 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Channel Capture/Compare Register – CHCCR

This register specifies the timer channel capture/compare value.

Offset: 0x090


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

CHCCV

10 9 8


7 6 5 4 3 2 1 0

CHCCV


Bits

[15:0]

Field

CHCCV

Descriptions

Channel Capture/Compare Value

- When Channel is configured as an output

The CHCCR value is compared with the counter value and the comparison result is used to trigger the CHOREF output signal.

- When Channel is configured as an input

The CHCCR register stores the counter value captured by the last channel capture event.

Rev. 1.00 546 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

25

Basic Function Timer (BFTM)

Introduction

The Basic Function Timer is a 32-bit up-counting counter designed to measure time intervals, generate one shot pulses or generate repetitive interrupts. The BFTM can operate in two modes which are repetitive and one shot modes. The repetitive mode restarts the counter at each compare match event which is generated by the internal comparator. The BFTM also supports a one shot mode which will force the counter to stop counting when a compare match event occurs.

OSM Counter

Controller

To A/D Converter

BFTM APB clock

EN CLR

32-bit Up-Counter Comparator

MIF

MIEN

To NVIC

BFTMCNTR

Figure 191. BFTM Block Diagram

BFTMCMPR

Features

▆

32-bit up-counting counter

▆

▆

▆

▆

▆

▆

▆

Compare Match function

Includes debug mode

Clock source: BFTM APB clock

Counter value can be Read/Written on the fly

One shot mode: counter stops counting when compare match occurs

Repetitive mode: counter restarts when compare match occurs

Compare Match interrupt enable/disable control

Rev. 1.00 547 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU


The BFTM is a 32-bit up-counting counter which is driven by the BFTM APB clock, PCLK. The counter value can be changed or read at any time even when the timer is counting. The BFTM supports two operating modes known as the repetitive mode and one shot mode allowing the measurement of time intervals or the generation of periodic time durations.

Repetitive Mode

The BFTM counts up from zero to a specific compare value which is pre-defined by the

BFTMCMPR register. When the BFTM operates in the repetitive mode and the counter reaches a value equal to the specific compare value in the BFTMCMPR register, the timer will generate a compare match event signal, MIF. When this occurs, the counter will be reset to 0 and resume its counting operation. When the MIF signal is generated, a BFTM compare match interrupt will also be generated periodically if the compare match interrupt is enabled by setting the corresponding interrupt control bit, MIEN, to 1. The counter value will remain unchanged and the counter will stop counting if it is disabled by clearing the CEN bit to 0.

0xFFFF_FFFF

CMP

Keep counter value when CEN is reset

Time

CNT

MIF

CEN

: Updated by software

Figure 192. BFTM – Repetitive Mode

: Cleared by software

Rev. 1.00 548 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

One Shot Mode

By setting the OSM bit in BFTMCR register to 1, the BFTM will operate in the one shot mode. The

BFTM starts to count when the CEN bit is set to 1 by the application program. The counter value will remain unchanged if the CEN bit is cleared to 0 by the application program. However, the counter value will be reset to 0 and stop counting when the CEN bit is cleared automatically to 0 by the internal hardware when a counter compare match event occurs.

CMP

CNT value unchanged when CEN is reset

By S/W

: Updated by software

: Cleared by software

: Cleared by hardware

Time

CNT

MIF

CEN

Figure 193. BFTM – One Shot Mode

0xFFFF_FFFF

CMP

CNT

MIF

Time

CEN

: Updated by software : Cleared by software

Figure 194. BFTM – One Shot Mode Counter Updating

: Cleared by hardware

Trigger ADC Start

When a BFTM compare match event occurs, a compare match interrupt flag, MIF, will be generated which can be used as an A/D Converter input trigger source.

Rev. 1.00 549 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Register Map

The following table shows the BFTM registers and reset values.

Table 68. BFTM Register Map

Register

BFTMCR

BFTMSR

BFTMCNTR

BFTMCMPR

Offset

0x000

0x004

0x008

0x00C

Description

BFTM Control Register

BFTM Status Register

BFTM Counter Value Register

BFTM Compare Value Register


BFTM Control Register – BFTMCR

This register specifies the overall BFTM control bits.

Offset: 0x000


31 30 29 28

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

21

13

5

Reserved

20

12

4

Reset Value

0x0000_0000

0x0000_0000

0x0000_0000

0xFFFF_FFFF

27

Reserved

19

Reserved

26

18

25

17

24

16

11

Reserved

3

10 9 8

2

CEN

1

OSM

0

MIEN

RW 0 RW 0 RW 0

Bits

[2]

[1]

[0]

Field

CEN

OSM

MIEN

Descriptions

BFTM Counter Enable Control

0: BFTM is disabled

1: BFTM is enabled

When this bit is set to 1, the BFTM counter will start to count. The counter will stop counting and the counter value will remain unchanged when the CEN bit is cleared to 0 by the application program regardless of whether it is in the repetitive or one shot mode. However, in the one shot mode, the counter will stop counting and be reset to 0 when the CEN bit is cleared to 0 by the timer hardware circuitry which results from a compare match event.

BFTM One Shot Mode Selection

0: Counter operates in repetitive mode

1: Counter operates in one shot mode

BFTM Compare Match Interrupt Enable Control

0: Compare Match Interrupt is disabled

1: Compare Match Interrupt is enabled

Rev. 1.00 550 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

BFTM Status Register – BFTMSR

This register specifies the BFTM status.

Offset: 0x004


31 30 29

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

21

13

5

28

20

27

Reserved

19

Reserved

12

4

Reserved

11

Reserved

3

Type/Reset

Bits

[0]

Field

MIF

26

18

10

25

17

9

24

16

8

2 1 0

MIF

W0C 0

Descriptions

BFTM Compare Match Interrupt Flag

0: No compare match event occurs

1: Compare match event occurs

When the counter value, CNT, is equal to the compare register value, CMP, a compare match event will occur and the corresponding interrupt flag, MIF will be set.

The MIF bit is cleared to 0 by writing a data “0”.

Rev. 1.00 551 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

BFTM Counter Value Register – BFTMCNTR

This register specifies the BFTM counter value.

Offset: 0x008


31 30 29 28 27

CNT

26 25 24


23 22 21 20 19

CNT

18 17 16


15 14 13 12 11

CNT

10 9 8


7 6 5 4 3 2 1 0

CNT


Bits

[31:0]

Field

CNT

Descriptions

BFTM Counter Value

A 32-bit BFTM counter value is stored in this field which can be read or written on the fly.

BFTM Compare Value Register – BFTMCMPR

The register specifies the BFTM compare value.

Offset: 0x00C

Reset value: 0xFFFF_FFFF

31 30 29 28 27

CMP

26 25 24


23 22 21 20 19

CMP

18 17 16


15 14 13 12 11

CMP

10 9 8


7 6 5 4 3

CMP

2 1 0


Bits

[31:0]

Field

CMP

Descriptions

BFTM Compare Value

This register specifies a 32-bit BFTM compare value which is used for comparison with the BFTM counter value.

Rev. 1.00 552 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

26

Watchdog Timer (WDT)

Introduction

The Watchdog Timer is a hardware timing circuitry that can be used to detect a system lock-up due to software trapped in a deadlock. The Watchdog Timer can be operated in a reset mode. The

Watchdog Timer will generate a reset when the counter counts down to a zero value. Therefore, the software should reload the counter value before a Watchdog Timer underflow occurs. In addition, a reset is also generated if the software reloads the counter before it reaches a delta value. That means that the Watchdog Timer prevents a software deadlock that continuously triggers the Watchdog, the reload must occur when the Watchdog Timer value has a value within a limited window of 0 and WDTD. The Watchdog Timer counter can be stopped when the processor is in the debug or the three sleep modes. The register write protection function can be enabled to prevent an unexpected change in the Watchdog Timer configuration.

WDTV

WDTRS

RSKEY[15:0]

LSI RC

32 kHz

LSE OSC

32.768 kHz

0

1

WDTEN

WDTSRC

CK_WDT

Clear

Prescaler

1, /2, /4, /8,

… /128

WPSC[2:0]

Reload

12-bit

Down-Counter

WDTD

Underflow

WDTUF

WDTERR

WDT Error

WDT_RSTn

WDTRSTEN

Read WDTSR Register

Figure 195. Watchdog Timer Block Diagram

Rev. 1.00 553 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Features

▆

▆

▆

▆

▆

▆

▆

▆

Clock source from either the internal 32 kHz RC oscillator (LSI) or the external 32,768 Hz oscillator (LSE)

Can be independently setup to keep running or to stop when entering the Sleep or Deep-Sleep1 mode

12-bit down-counter with 3-bit prescaler structure

Provides reset to the system

Limited reload window setup function for custom Watchdog Timer reload times

Watchdog Timer may be stopped when the processor is in the debug mode

Reload lock key to prevent unexpected operation

Configuration register write protection function for counter value, reset enable, delta value, and prescaler value


The Watchdog Timer is formed from a 12-bit count-down counter and a fixed 3-bit prescaler. The largest time-out period is 16 seconds, using the LSE or LSI clock and a 1/128 maximum prescaler value.

The Watchdog Timer configuration setup includes programmable counter reload value, reset enable, window value and prescaler value. These configurations are set using the WDTMR0 and WDTMR1 registers which must be properly programmed before the Watchdog Timer starts counting. In order to prevent unexpected write operations to those configurations, a register write protection function can be enabled by writing any value, other than 0x35CA to PROTECT[15:0], in the WDTPR register. A value of 0x35CA can be written to PROTECT[15:0] to disable the register write protection function before accessing any configuration register. A read operation on

PROTECT[0] can obtain the enable/disable status of the register write protection function.

During normal operation, the Watchdog Timer counter should be reloaded before it underflows to prevent the generation of a Watchdog reset. The 12-bit count-down counter can be reloaded with the required Watchdog Timer Counter Value (WDTV) by first setting the WDTRS bit to1 with the correct key, which is 0x5FA0 in the WDTCR register.

If a software deadlock occurs during a Watchdog Timer reload routine, the reload operation will still go ahead and therefore the software deadlock cannot be detected. To prevent this situation from occurring, the reload operation must be executed in such a way that the value of the Watchdog

Timer counter is limited to within a delta value (WDTD). If the Watchdog Timer counter value is greater than the delta value and a reload operation is executed, a Watchdog Timer error will occur.

The Watchdog Timer error will cause a Watchdog reset if the related functional control is enabled.

Additionally, the above features can be disabled by programming a WDTD value greater than or equal to the WDTV value.

The WDTERR and WDTUF flags in the WDTSR register will be set respectively when the

Watchdog Timer error occurs or when a Watchdog Timer underflows. A system reset or writing “1” operation on the WDTSR register will clear the WDTERR and WDTUF flags.

The Watchdog Timer uses two clocks: PCLK and CK_WDT. The PCLK clock is used for APB access to the watchdog registers. The CK_WDT clock is used for the Watchdog Timer functionality and counting. There is some synchronization logic between these two clock domains.

Rev. 1.00 554 of 637 December 28, 2020

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Cortex ® -M0+ MCU

When the system enters the Sleep mode or Deep-Sleep1 mode, the Watchdog Timer counter will either continue to count or stop depending on the WDTSHLT field setup in the WDTMR0 register.

However, the Watchdog Timer will always stop when the system is in the Deep-Sleep2 mode.

When the Watchdog stops counting, the count value is retained so that it continues counting after the system is woken up from these three sleep modes. A Watchdog reset will occur any time when the Watchdog Timer is running and when it has an operating clock source. When the system enters the debug mode, the Watchdog Timer counter will either continue to count or stop depending on the DBWDT bit of the MCUDBGCR register in the Clock Control Unit.

The Watchdog timer should be used in the following manners:

▆

▆

▆

▆

▆

Set the Watchdog Timer reload value (WDTV) and reset in the WDTMR0 register.

Set the Watchdog Timer delta value (WDTD) and prescaler in the WDTMR1 register.

Start the Watchdog Timer by writing to the WDTCR register with WDTRS = 1 and RSKEY =

0x5FA0.

Write to the WDTPR register to lock all the Watchdog Timer registers except for WDTCR and

WDTPR.

The Watchdog Timer counter should be reloaded again within the delta value (WDTD).

Counter value

0xFFF

Reset occurred

(If WDTRSTEN = 1)

Reset not occurred

(If WDTRSTEN = 0)

WDTV

Reload is not allowed

WDTD

. . .

Reload is allowed

0

Start counter

Reload counter when counter ≤ WDTD

Normal behavior

Figure 196. Watchdog Timer Behavior

Reload counter when counter > WDTD

Watchdog Timer error

Watchdog Timer underflow

Time

Rev. 1.00 555 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Register Map

The following table shows the Watchdog Timer registers and reset values.

Table 69. Watchdog Timer Register Map

Register Offset

WDTCR 0x000

WDTMR0

WDTMR1

0x004

0x008

WDTSR

WDTPR

WDTCSR

0x00C

0x010

0x018

Description

Watchdog Timer Control Register

Watchdog Timer Mode Register 0

Watchdog Timer Mode Register 1

Watchdog Timer Status Register

Watchdog Timer Protection Register

Watchdog Timer Clock Selection Register

Reset Value

0x0000_0000

0x0000_0FFF

0x0000_7FFF

0x0000_0000

0x0000_0000

0x0000_0000


Watchdog Timer Control Register – WDTCR

This register is used to reload the Watchdog timer.

Offset: 0x000


31

23

30

22

29

21

28

20

27

RSKEY

26 25 24


19

RSKEY

18 17 16


15 14 13 12 11

Reserved

10 9 8

Type/Reset

Type/Reset

7 6 5 4

Reserved

3 2 1 0

WDTRS

WO 0

Bits

[31:16]

[0]

Field

RSKEY

WDTRS

Descriptions

Watchdog Timer Reload Lock Key

The RSKEY [15:0] bits should be written with a 0x5FA0 value to enable the WDT reload operation function. Writing any other value except 0x5FA0 in this field will abort the write operation.

Watchdog Timer Reload

0: No effect

1: Reload Watchdog Timer

This bit is used to reload the Watchdog timer counter as a WDTV value which is stored in the WDTMR0 register. It is set to 1 by software and cleared to 0 by hardware automatically.

Rev. 1.00 556 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Watchdog Timer Mode Register 0 – WDTMR0

This register specifies the Watchdog timer counter reload value and reset enable control.

Offset: 0x004

Reset value: 0x0000_0FFF

31 30 29 28 27

Reserved

26 25 24

Type/Reset

Type/Reset

23 22 21 20 19

Reserved

18 17 16

WDTEN

RW 0

15 14 13 12

WDTSHLT WDTRSTEN Reserved

Type/Reset RW 0 RW 0 RW 0

7 6 5 4

11 10 9

WDTV

8

RW 1 RW 1 RW 1 RW 1

3 2 1 0

WDTV


Bits

[16]

[15:14]

[13]

[11:0]

Field

WDTEN

Descriptions

Watchdog Timer Running Enable

0: Watchdog Timer is disabled

1: Watchdog Timer is enabled to run

When the Watchdog Timer is disabled, the counter will be reset to its hardware default condition. When the WDTEN bit is set, the Watchdog Timer will be reloaded with the WDTV value and count down.

WDTSHLT Watchdog Timer Sleep Halt

00: The Watchdog runs when the system is in the Sleep mode or Deep-Sleep1 mode

01: The Watchdog runs when the system is in the Sleep mode and halts in Deep-

Sleep1 mode

10 or 11: The Watchdog halts when the system is in the Sleep mode and Deep-

Sleep1 mode

Note that the Watchdog timer always halts when the system is in the Deep-

Sleep2 mode. The Watchdog stops counting when the WDTSHLT field is properly configured in the Sleep mode or Deep-Sleep1 mode. When the Watchdog stops counting, the count value is retained so that it continues counting after the system wakes up from these three sleep modes. If a Watchdog reset occurs in the Sleep or

Deep-Sleep1 mode, it will wake up the device.

WDTRSTEN Watchdog Timer Reset Enable

0: A Watchdog Timer underflow or error has no effect on the system reset

1: A Watchdog Timer underflow or error triggers a Watchdog Timer system reset

WDTV Watchdog Timer Counter Value

WDTV defines the value loaded into the 12-bit Watchdog down-counter.

Rev. 1.00 557 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Watchdog Timer Mode Register 1 – WDTMR1

This register specifies the Watchdog delta value and the prescaler selection.

Offset: 0x008

Reset value: 0x0000_7FFF

31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

Type/Reset

15

Reserved

7

14

6

13

WPSC

5

12

4

11

3

10

2

9

WDTD

1

8

RW 1 RW 1 RW 1 RW 1 RW 1 RW 1 RW 1

0

WDTD


Bits

[14:12]

[11:0]

Field

WPSC

WDTD

Descriptions

Watchdog Timer Prescaler Selection

000: 1/1

001: 1/2

010: 1/4

011: 1/8

100: 1/16

101: 1/32

110: 1/64

111: 1/128

Watchdog Timer Delta Value

Define the permitted range to reload the Watchdog Timer. If the Watchdog Timer counter value is less than or equal to WDTD, writing to the WDTCR register with

WDTRS = 1 and RSKEY = 0x5FA0 will reload the timer. If the Watchdog Timer value is greater than WDTD, then writing WDTCR with WDTRS = 1 and RSKEY = 0x5FA0 will cause a Watchdog Timer error. This feature can be disabled by programming a

WDTD value greater then or equal to the WDTV value.

Rev. 1.00 558 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Watchdog Timer Status Register – WDTSR

This register specifies the Watchdog timer status.

Offset: 0x00C


31 30 29

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

21

13

5

28

20

27

Reserved

19

Reserved

12

4

Reserved

11

Reserved

3

Type/Reset

Bits

[1]

[0]

26

18

10

25

17

9

24

16

8

2 1 0

WDTERR WDTUF

WC 0 WC 0

Field

WDTERR

WDTUF

Descriptions

Watchdog Timer Error

0: No Watchdog Timer error has occurred since the last read of this register

1: A Watchdog Timer error has occurred since the last read of this register

Note: A reload operation when the Watchdog Timer counter value is larger than

WDTD causes a Watchdog Timer error. Note that this bit is a write-one-clear flag.

Watchdog Timer Underflow

0: No Watchdog Timer underflow has occurred since the last read of this register

1: A Watchdog Timer underflow has occurred since the last read of this register

Note that this bit is a write-one-clear flag.

Rev. 1.00 559 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Watchdog Timer Protection Register – WDTPR

This register specifies the Watchdog timer protect key configuration.

Offset: 0x010


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

PROTECT

10 9 8


7 6 5 4 3 2 1 0

PROTECT


Bits

[15:0]


PROTECT Watchdog Timer Register Protection

For write operation:

0x35CA: Disable the Watchdog Timer register write protection

Others: Enable the Watchdog Timer register write protection

For read operation:

0x0000: Watchdog Timer register write protection is disabled

0x0001: Watchdog Timer register write protection is enabled

This register is used to enable/disable the Watchdog timer configuration register write protection function. All configuration registers become read only except for

WDTCR and WDTPR when the register write protection is enabled. Additionally, the read operation of PROTECT[0] can obtain the enable/disable status of the register write protection function.

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32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Watchdog Timer Clock Selection Register – WDTCSR

This register specifies the Watchdog timer clock source selection and lock configuration.

Offset: 0x018


31 30 29

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

Reserved

21

13

5

28

20

27

Reserved

19

Reserved

26

18

12

4

WDTLOCK

RW 0

11

Reserved

3

10

2

Reserved

Bits

[4]

[0]

25

17

9

24

16

8

1 0

WDTSRC

RW 0


WDTLOCK Watchdog Timer Lock Mode

0: This bit is only set to 0 on any reset. It can not be cleared by software.

1: This bit is set once only by software and locks the Watchdog Timer function.

Software can set this bit to 1 at any time. Once the WDTLOCK bit is set, the function and registers of the Watchdog Timer cannot be modified or disabled, including the

Watchdog Timer clock source. The lock mode can only be disabled until a system reset occurs.

WDTSRC Watchdog Timer Clock Source Selection

0: Internal 32 kHz RC oscillator clock is selected (LSI)

1: External 32.768 kHz crystal oscillator clock is selected (LSE)

Select using software to control the Watchdog timer clock source.

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Cortex ® -M0+ MCU

27

Real Time Clock (RTC)

Introduction

The Real Time Clock, RTC, circuitry includes the APB interface, a 24-bit up-counter, a control register, a prescaler, a compare register and a status register. Most of the RTC circuits are located in the V

DD

Power Domain, as shown in dotted red box in the accompanying figure, except for the APB interface. The APB interface is located in the V

DD15

domain. Therefore, it is necessary to be isolated by the ISO signal that comes from the power control unit when the V

DD15

domain is powered off, i.e., when the device enters the Power-Down mode. The RTC counter is used as a wakeup timer to let the system resume from the power-saving modes. The detailed RTC function will be described in the following sections.

LSE

OSC

CK_LSE

1

LSI RC

OSC

CK_LSI

0

RTCSRC

CK_RTC

ISO

APB Bus

APB Interface and

ISO & Level Shift

Prescaler

CK_SECOND

24-bit Counter

CMPCLR

Compare

Register

24

Match

24

V

DD

Power Domain V

DD

1.5 V Core Power Domain V

DD15 set

CSECFLAG set set

OVFLAG

CMFLAG

Figure 197. RTC Block Diagram

CSECIEN

OVIEN

CMIEN

CSECWEN

OVWEN

CMWEN

RTCINT

( To NVIC )

RTCWAKEUP

( To EXTI and PWRCU )

Features

▆

24-bit up-counter for counting elapsed time

▆

▆

▆

▆

▆

Programmable clock prescaler

● Division factor: 1, 2, 4, 8…, 32768

24-bit compare register for alarm usage

RTC clock source

● LSE oscillator clock

● LSI oscillator clock

Three RTC Interrupt/wakeup settings

● RTC second clock interrupt/wakeup

● RTC compare match interrupt/wakeup

● RTC counter overflow interrupt/wakeup

The RTC interrupt/wakeup event can work together with power management to wake up the chip from power saving mode

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Cortex ® -M0+ MCU


RTC Related Register Reset

The RTC registers can only be reset by either a V

Domain software reset by setting the PWRST bit in the PWRCR register. Other reset events have no effect to clear the RTC registers.

DD

Domain power on reset, POR, or by a V

DD

Reading RTC Register

The RTC control logic and the related registers are powered by the V the APB bus, which is located in the V in the V

DD15

DD

supply voltage. Therefore, the RTC circuitry remains operational in the Power-Down mode where V

DD15

is powered off. Only

domain, is interconnected to the RTC circuits located

DD

domain using level shift circuitry and isolated by the ISO signals when the V

DD15

supply voltage is powered off.

Low Speed Clock Configuration

The default RTC clock source, CK_RTC, is derived from the LSI oscillator. The CK_RTC clock can be derived from either the external 32768 Hz crystal oscillator, named the LSE oscillator, or the internal 32K RC oscillator named the LSI oscillator, by setting the RTCSRC bit in the RTCCR register. A prescaler is provided to divide the CK_RTC by a ratio ranged from 2 0 to 2 15 determined by the RPRE [3:0] field. For instance, setting the prescaler value RPRE [3:0] to 0xF will generate an exact 1 Hz CK_SECOND clock if the CK_RTC clock frequency is equal to 32,768 Hz. The

LSE oscillator can be enabled by the LSEEN control bit in the RTCCR register. In addition, the

LSE oscillator startup mode can be selected by configuring the LSESM bit in the RTCCR register.

This enables the LSE oscillator to have either a shorter startup time or a lower power consumption, both of which are traded off depending upon specific application requirements. An example of the startup time and the power consumption for different startup modes are shown in the accompanying table for reference.

Table 70. LSE Startup Mode Operating Current and Startup Time

Startup Mode

Normal startup

LSESM Setting in the RTCCR Register

0

Operating Current

2.0 μA

Startup Time

Above 500 ms

Fast startup 1 3.5 μA Below 300 ms

@ V

DD

= 3.3 V and LSE clock = 32,768 Hz; these values are only for reference, actual values are dependent on the specification of the external 32.768 kHz crystal.

Rev. 1.00 563 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

RTC Counter Operation

The RTC provides a 24-bit up-counter which increases at the falling edge of the CK_SECOND clock and whose value can be read from the RTCCNT register asynchronously via the APB bus.

A 24-bit compare register, RTCCMP, is provided to store the specific value to be compared with the RTCCNT content. This is used to define a pre-determined time interval. When the RTCCNT register content is equal to the RTCCMP register value, the match flag CMFLAG in the RTCSR register will be set by hardware and an interrupt or wakeup event can be sent according to the corresponding enable bits in the RTCIWEN register. The RTC counter will be either reset to zero or keep counting when the compare match event occurs, dependent upon the CMPCLR bit in the RTCCR register. For example, if the RPRE [3:0] is set to 0xF, the RTCCMP register content is set to a decimal value of 60 and the CMPCLR bit is set to 1, then the CMFLAG bit will be set every minute. In addition, the OVFLAG bit in the RTCSR register will be set when the RTC counter overflows. A read operation on the RTCSR register clears the status flags including the

CSECFLAG, CMFLAG and OVFLAG bits.

Interrupt and Wakeup Control

The falling edge of the CK_SECOND clock causes the CSECFLAG bit in the RTCSR register to be set and generates an interrupt if the corresponding interrupt enable bit, CSECIEN, in the

RTCIWEN register is set. The wakeup event can also be generated to wake up the HSI/HSE oscillators, the PLL circuitry, the LDO and the CPU core if the corresponding wakeup enable bit CSECWEN is set. When the RTC counter overflows or a compare match event occurs, it will generate an interrupt or a wake up event determined by the corresponding interrupt or wakeup enable control bits, OVIEN/OVWEN or CMIEN/CMWEN bits, in the RTCIWEN register. Refer to the related register definitions for more details.

RTCOUT Output Pin Configuration

The following table shows the RTCOUT output format according to the mode, polarity, and event selection setting.

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HT32F5828

Cortex ® -M0+ MCU

Table 71. RTCOUT Output Mode and Active Level Setting

ROWM ROES RTCOUT Output Waveform

1

(Level mode)

0

(Compare match)

1

(Second clock)

0

(Compare match)

1

(Second clock)

RTCCMP

RTCCNT

RTCOUT (ROAP = 0)

RTCOUT (ROAP = 1)

ROLF

3

T

R

0

(Pulse mode)

RTCCMP

RTCCNT 3

T

R

T

RTCOUT (ROAP = 0)

RTCOUT (ROAP = 1)

ROLF

R

RTCCMP

RTCCNT

RTCOUT (ROAP = 0)

RTCOUT (ROAP = 1)

ROLF

RTCCMP

RTCCNT

RTCOUT (ROAP = 0)

RTCOUT (ROAP = 1)

ROLF

T

R

: RTCOUT output pulse time = 1 / f

CK_RTC

→: Cleared by software reading ROLF bit

3

3

→ →

4

4

X

4

4

4

4

X

T

R

→

5

5

5

5

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HT32F5828

Cortex ® -M0+ MCU

Register Map

The following table shows the RTC registers and reset values. Note all the registers in this unit are located at the V

DD

power domain.

Table 72. RTC Register Map

Register Offset

RTCCNT 0x000

Description

RTC Counter Register

RTCCMP

RTCCR

RTCSR

0x004

0x008

0x00C

RTCIWEN 0x010

RTC Compare Register

RTC Control Register

RTC Status Register

RTC Interrupt and Wakeup Enable Register

Reset Value

0x0000_0000

0x0000_0000

0x0000_0F04

0x0000_0000

0x0000_0000


RTC Counter Register – RTCCNT

This register defines a 24-bit up-counter which is increased by the CK_SECOND clock.

Address: 0x000

Reset value: 0x0000_0000 (Reset by V

DD

Power Domain reset only)

31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

RTCCNTV

18 17 16


15 14 13 12 11

RTCCNTV

10 9 8


7 6 5 4 3

RTCCNTV

2 1 0


Bits

[23:0]


RTCCNTV RTC Counter Value

The current value of the RTC counter is returned when reading the RTCCNT register. The RTCCNT register is updated during the falling edge of the CK_

SECOND clock. This register is reset by one of the following conditions:

- V

- V

DD

Domain software reset – set the PWRST bit in the PWRCR register

DD

Domain power on reset – POR

- Compare match (RTCCNT = RTCCMP) when CMPCLR = 1 (in the RTCCR register)

- RTCEN bit changed from 0 to 1

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HT32F5828

Cortex ® -M0+ MCU

RTC Compare Register – RTCCMP

This register defines a specific value to be compared with the RTC counter value.

Address: 0x004


DD


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

RTCCMPV

18 17 16


15 14 13 12 11

RTCCMPV

10 9 8


7 6 5 4 3 2 1 0

RTCCMPV


Bits

[23:0]


RTCCMPV RTC Compare Match Value

A match condition happens when the value in the RTCCNT register is equal to the

RTCCMP value. An interrupt can be generated if the CMIEN bit in the RTCIWEN register is set. When the CMPCLR bit in the RTCCR register is set to 0 and a match condition happens, the CMFLAG bit in the RTCSR register is set while the value in the RTCCNT register is not affected and will continue to count until overflow. When the CMPCLR bit is set to 1 and a match condition happens, the CMFLAG bit in the

RTCSR register is set and the RTCCNT register will be reset to zero and then the counter continues to count.

Rev. 1.00 567 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

RTC Control Register – RTCCR

This register specifies a range of RTC circuitry control bits.

Address: 0x008

Reset value: 0x0000_0F04 (Reset by V

DD


31

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

30 29 28 27

Reserved

26 25 24

22

Reserved

21 20

ROLF

19

ROAP

18

ROWM

17

ROES

16

ROEN

RC 0 RW 0 RW 0 RW 0 RW 0

14 13

Reserved

12 11 10 9

RPRE

8

6 5 4

RW 1 RW 1 RW 1 RW 1

3 2 1 0

Reserved LSESM CMPCLR LSEEN Reserved RTCSRC RTCEN


Bits

[20]

[19]

[18]

[17]

[16]

Field

ROLF

ROAP

ROWM

ROES

ROEN

Descriptions

RTCOUT Level Mode Flag

0: RTCOUT Output is inactive

1: RTCOUT Output is holding as active level

Set by hardware when in the level mode (ROWM = 1) and a RTCOUT output event occurs. Cleared by software reading this flag. The RTCOUT signal will return to the inactive level after software has read this bit.

RTCOUT Output Active Polarity

0: Active level is high

1: Active level is low

RTCOUT Output Waveform Mode

0: Pulse mode

The output pulse duration is one RTC clock (CK_RTC) period.

1: Level mode

The RTCOUT signal will remain at an active level until the ROLF bit is cleared by software reading the ROLF bit.

RTCOUT Output Event Selection

0: RTC compare match is selected

1: RTC second clock (CK_SECOND) event is selected

The ROES bit can be used to select whether the RTCOUT signal is output on the

RTCOUT pin when a RTC compare match event or the RTC second clock (CK_

SECOND) event occurs.

RTCOUT Output Pin Enable

0: Disable RTCOUT output pin

1: Enable RTCOUT output pin

When the ROEN bit is set to 1, the RTCOUT signal will be at an active level once a RTC compare match or the RTC second clock (CK_SECOND) event occurs. The active polarity and output waveform mode can be configured by the ROAP and

ROWM bits respectively. When the ROEN bit is cleared to 0, the RTCOUT pin will be in a floating state.

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HT32F5828

Cortex ® -M0+ MCU

[5]

[4]

[3]

[1]

[0]

Bits

[11:8]

Field

RPRE

LSESM

CMPCLR

LSEEN

RTCSRC

RTCEN

Descriptions

RTC Clock Prescaler Select

CK_SECOND = CK_RTC / 2 RPRE

0000: CK_SECOND = CK_RTC / 2 0



…


LSE oscillator Startup Mode

0: Normal startup and requires less operating power

1: Fast startup but requires higher operating current

Compare Match Counter Clear

0: 24-bit RTC counter is not affected when compare match condition occurs

1: 24-bit RTC counter is cleared when compare match condition occurs

LSE oscillator Enable Control

0: LSE oscillator is disabled

1: LSE oscillator is enabled

RTC Clock Source Selection

0: LSI oscillator is selected as the RTC clock source

1: LSE oscillator is selected as the RTC clock source

RTC Enable Control

0: RTC is disabled

1: RTC is enabled

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HT32F5828

Cortex ® -M0+ MCU

RTC Status Register – RTCSR

This register stores the counter flags.

Address: 0x00C


DD

Power Domain reset and RTCEN bit change from 1 to 0)

31 30 29 28

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

21

13

5

Reserved

20

12

4

27

Reserved

19

Reserved

26

18

25

17

24

16

11

Reserved

3

10 9 8

2 1 0

OVFLAG CMFLAG CSECFLAG

RC 0 RC 0 RC 0

Bits

[2]

[1]

[0]


OVFLAG

CMFLAG

Counter Overflow Flag

0: Counter overflow has not occurred since the last RTCSR register read operation

1: Counter overflow has occurred since the last RTCSR register read operation

This bit is set by hardware when the counter value in the RTCCNT register changes from 0x00FF_FFFF to 0x0000_0000 and cleared by read operation. This bit is suggested to be read in the RTC IRQ handler and should be taken care when software polling is used.

Compare Match Condition Flag

0: Compare match condition has not occurred since the last RTCSR register read operation

1: Compare match condition has occurred since the last RTCSR register read operation.

This bit is set by hardware on the CK_SECOND clock falling edge when the

RTCCNT register value is equal to the RTCCMP register content. It is cleared by software reading this bit. This bit is suggested for access in the corresponding RTC interrupt routine – do not use software polling during software free running.

CSECFLAG CK_SECOND Occurrence Flag

0: CK_SECOND has not occurred since the last RTCSR register read operation

1: CK_SECOND has occurred since the last RTCSR register read operation

This bit is set by hardware on the CK_SECOND clock falling edge. It is cleared by software reading this bit. This bit is suggested for access in the corresponding RTC interrupt routine – do not use software polling during software free running.

Rev. 1.00 570 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

RTC Interrupt and Wakeup Enable Register – RTCIWEN

This register contains the interrupt and wakeup enable bits.

Address: 0x010


DD


31 30 29 28

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

21

13

Reserved

5

Reserved

20

12

4

27

Reserved

19

Reserved

11

3

26

18

25

17

24

16

10 9 8

OVWEN CMWEN CSECWEN

RW 0 RW 0 RW 0

2 1 0

OVIEN CMIEN CSECIEN

RW 0 RW 0 RW 0

Bits

[10]

[9]

[8]

[2]

[1]

[0]


OVWEN

CMWEN

Counter Overflow Wakeup Enable

0: Counter overflow wakeup is disabled

1: Counter overflow wakeup is enabled

Compare Match Wakeup Enable

0: Compare match wakeup is disabled

1: Compare match wakeup is enabled

CSECWEN Counter Clock CK_SECOND Wakeup Enable

0: Counter Clock CK_SECOND wakeup is disabled

1: Counter Clock CK_SECOND wakeup is enabled

OVIEN Counter Overflow Interrupt Enable

0: Counter Overflow Interrupt is disabled

1: Counter Overflow Interrupt is enabled

CMIEN Compare Match Interrupt Enable

0: Compare Match Interrupt is disabled

1: Compare Match Interrupt is enabled

CSECIEN Counter Clock CK_SECOND Interrupt Enable

0: Counter Clock CK_SECOND Interrupt is disabled

1: Counter Clock CK_SECOND Interrupt is enabled

Rev. 1.00 571 of 637 December 28, 2020

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Cortex ® -M0+ MCU

28

Cyclic Redundancy Check (CRC)

Introduction

The CRC (Cyclic Redundancy Check) calculation unit is an error detection technique test algorithm and is used to verify data transmission or storage data correctness. A CRC calculation takes a data stream or a block of data as input and generates a 16-bit or 32-bit output remainder. Ordinarily, a data stream is suffixed by a CRC code and used as a checksum when being sent or stored.

Therefore, the received or restored data stream is calculated by the same generator polynomial as described above. If the new CRC code result does not match the one calculated earlier, that means data stream contains a data error.

CRC Control

Register

CRC Seed

Register

CRC Data

Register

B3

B2

B1

B0

MUX

1's

COMP

BIT

REVERSE

CCITT-16

POLY

CRC-16

POLY

CRC-32

POLY

MUX

MUX

CRC FSM

CRC

REG

1's

COMP

BIT

REVERSE

BYTE

REVERSE

CRC Sum

Register

BYTE

REVERSE

Figure 198. CRC Block Diagram

Features

▆

Supports CRC16 polynomial: 0x8005, X 16 + X 15 + X 2 + 1

▆

▆

▆

▆

▆

▆

▆

Supports CCITT CRC16 polynomial: 0x1021, X 16 + X 12 + X 5 + 1

Supports IEEE-802.3 CRC32 polynomial: 0x04C11DB7, X 32

+ X 10 + X 8 + X 7 + X 5 + X 4 + X 2 + X + 1

+ X 26 + X 23 + X 22 + X 16 + X 12 + X 11

Supports 1’s complement, byte reverse and bit reverse operation on data and checksum

Supports byte, half-word and word data size

Programmable CRC initial seed value

CRC computation done in 1 AHB clock cycle for 8-bit data and 4 AHB clock cycles for 32-bit data

Supports PDMA to complete a CRC computation of a block of memory

Rev. 1.00 572 of 637 December 28, 2020

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Cortex ® -M0+ MCU


This unit only enables the calculation in the CRC16, CCITT CRC16 and IEEE-802.3 CRC32 polynomials. In this unit, the generator polynomial is fixed to the numeric values for those modes; therefore, the CRC value based on other generator polynomials cannot be calculated.

CRC Computation

The CRC calculation unit has a 32-bit write CRC data register (CRCDR) and a read CRC checksum register (CRCCSR). The CRCDR register is used to input new data (write access) and the CRCCSR register is used to hold the result of the previous CRC calculation (read access). Each write operation to the CRCDR register creates a combination of the previous CRC value (stored in CRCCSR) and the new one. The CRC block diagram is shown as Figure 198. The CRC unit calculates the CRC data register (CRCDR) value byte by byte and the default byte and bit order is big-endian. The CRCDR register can be written by word, right-aligned half-word and right-aligned byte. For the other registers only 32-bit access is allowed. The duration of the computation depends on data width:

▆

▆

▆

4 AHB clock cycles for 32-bit data input

2 AHB clock cycles for 16-bit data input

1 AHB clock cycle for 8-bit data input

Byte and Bit Reversal for CRC Computation

The byte reordering and byte-level bit reversal operation can be occurred before the data is used in the CRC calculation or after the CRC checksum output. They are configurable using the corresponding setting field of the CRCCR register. These operations occur on word or half-word writes. The hardware ignores the DATBYRV bit of the CRCCR register during any byte writes but the bit reversal setting DATBIRV are still applied to the byte. Figure 199 shows the byte and bit reversal operation example.

Byte 3 Byte 2 Byte 1 Byte 0

Input data is big-endian

Byte Reversal Enable

Byte 0 Byte 1 Byte 2 Byte 3

Bit Reversal Enable

Byte 0 Byte 1

Figure 199. CRC Data Bit and Byte Reversal Example

Rev. 1.00 573 of 637

Byte 2 Byte 3

December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

CRC with PDMA

A PDMA channel with software trigger may be used to transfer data into the CRC unit. If a huge block data needs to be calculated, the recommended PDMA model is to use the PDMA to transfer all available words of data and use software writes to transfer the other remaining bytes. To write data into the CRC unit, the PDMA should use word access method to transfer data from the source location of memory to the CRC data register (CRCDR) in fixed address mode. Then software can write any remaining bytes to the CRC data register (CRCDR) and read the CRC calculation result value from the CRC checksum register (CRCCSR).

Register Map

The following table shows the CRC registers and reset values.

Table 73. CRC Register Map

Register Offset

CRCCR 0x000

Description

CRC Control Register

CRCSDR

CRCCSR

CRCDR

0x004

0x008

0x00C

CRC Seed Register

CRC Checksum Register

CRC Data Register

Reset Value

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000


CRC Control Register – CRCCR

This register specifies the corresponding CRC function enable control.

Offset: 0x000


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

Reserved

10 9 8

Type/Reset

7 6 5 4 3 2

SUMCMPL SUMBYRV SUMBIRV DATCMPL DATBYRV DATBIRV

1 0

POLY


Bits

[7]

[6]


SUMCMPL 1’s Complement operation on Checksum Output

0: Disable

1: Enable

SUMBYRV Byte Reverse operation on Checksum Output

0: Disable

1: Enable

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32-Bit Arm ®

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Cortex ® -M0+ MCU

Bits

[5]

[4]

[3]

[2]

[1:0]

Field

SUMBIRV

DATCMPL

DATBYRV

DATBIRV

POLY

Descriptions

Bit Reverse operation on Checksum Output

0: Disable

1: Enable

1’s Complement operation on Data

0: Disable

1: Enable

Byte Reverse operation on Data

0: Disable

1: Enable

Bit Reverse operation on Data

0: Disable

1: Enable

CRC polynomial

00: CRC-CCITT (0x1021)

01: CRC-16 (0x8005)

1x: CRC-32 (0x04C11DB7)

CRC Seed Register – CRCSDR

This register is used to specify the CRC seed.

Offset: 0x004


31 30 29 28 27

SEED

26 25 24


23 22 21 20 19 18 17 16

SEED


15 14 13 12 11

SEED

10 9 8


7 6 5 4 3

SEED

2 1 0


Bits

[31:0]

Field

SEED

Descriptions

CRC Seed Data

Put the 16/32-bit seed value in this register according to the polynomial setting in the CRCCR register.

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Cortex ® -M0+ MCU

CRC Checksum Register – CRCCSR

This register contains the CRC checksum output.

Offset: 0x008


31 30 29 28 27

CHKSUM

26 25 24


23 22 21 20 19

CHKSUM

18 17 16


15 14 13 12 11

CHKSUM

10 9 8


7 6 5 4 3 2 1 0

CHKSUM


Bits

[31:0]

Field

CHKSUM

Descriptions

CRC Checksum Data

Get the CRC 16/32-bit checksum result from this register according to the polynomial setting in the CRCCR register after all data are written to the CRCDR register.

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HT32F5828

Cortex ® -M0+ MCU

CRC Data Register – CRCDR

This register is used to specify the CRC input data.

Offset: 0x00C


31 30 29 28 27

CRCDATA

26 25 24


23 22 21 20 19

CRCDATA

18 17 16


15 14 13 12 11

CRCDATA

10 9 8


7 6 5 4 3 2 1 0

CRCDATA


Bits

[31:0]


CRCDATA CRC Input Data

Byte, half-word and word writes are allowed. 1’s complement, byte reverse and bit reverse operation can be applied.

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Cortex ® -M0+ MCU

29

Peripheral Direct Memory Access (PDMA)

Introduction

The Peripheral Direct Memory Access circuitry, PDMA, provides 6 unidirectional channels for dedicated peripherals to implement the peripheral-to-memory and memory-to-peripheral data transfer. The memory-to-memory data transfer such as the FLASH-to-SRAM or SRAM-to-

SRAM type is also supported and requested by the application program. Each PDMA channel configuration is independent. The PDMA channel transfer is split into multiple block transactions and the size of a block is equal to the block length multiplied by the data width.

Features

▆

▆

▆

▆

▆

▆

▆

6 unidirectional PDMA channels

Memory-to-peripheral, peripheral-to-memory and memory-to-memory data transfer

8-bit, 16-bit and 32-bit width data transfer

Software and hardware requested data transfer with configurable channel priority

Linear address, circular address and fixed address modes

4 transfer event flags – Transfer Complete, Half Transfer, Block End and Transfer Error

Auto-Reload function

AHB Slave

Interface

Channel Logic &

Registers

AHB Master

Interface

Figure 200. PDMA Block Diagram

PDMA

Req. & Ack

Interface

Control Logic &

Registers

Transfer

Interrupts

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HT32F5828

Cortex ® -M0+ MCU


AHB Master

The PDMA is an AHB master connected to other AHB peripherals such as the FLASH memory, the SRAM memory and the AHB-to-APB bridges through the bus-matrix. The CPU and PDMA can access different AHB slaves at the same time via the bus-matrix.

PDMA Channel

There are 6 unidirectional PDMA channels used to support data transfer between the peripherals and the memory. The configuration and operation of each PDMA channel is independent. For a bidirectional transfer application, two PDMA channels are required. Each PDMA channel is designed to support the dedicated multiple peripherals with the same registers. Therefore, one

PDMA channel only can service one peripheral at the same time. The related registers of the

PDMA channel are limited to be accessed with 32-bit operation; otherwise a system hard fault event will occur.

PDMA Request Mapping

The multiple requests from the peripherals (ADC, SPI, I 2 C, USART and so on) are simply logically

ANDed before entering the PDMA, which means that only one request must be enabled at a time in each PDMA channel. Refer to Figure 79 – PDMA request mapping architecture and detailed peripheral IP requests mapping table is shown as the Table 47. The peripheral DMA requests can be independently activated/de-activated by programming the DMA control bit in the registers of the corresponding peripheral.

IP1

Peripheral request signals

CH0 H/W REQ

IPn

CH0 S/W REQ

0

Channel 0

1

SWTRIG Enable

Channel 1

High priority

Channel 2 PDMA

Request

IPx

IPy

CHn H/W REQ

CHn S/W REQ

0

1

Channel n

Figure 201. PDMA Request Mapping Architecture

SWTRIG Enable

Low priority

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32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Table 74. PDMA Channel Assignments

IP

(x = 0, 1) CH0

ADC

CH1

PDMA Channel Number

CH2 CH3

ADC

SPIx

USART

UARTx

SCIx

I 2 Cx

GPTM

PWMx

I 2 S

AES

USR_RX

GT_CH1

GT_CH3

PWM0_CH1

PWM0_CH3

USR_TX

GT_CH2

GT_UEV

PWM0_CH2

PWM0_UEV

I2S_RX

SPI0_RX

UR0_RX

SCI1_RX

I2C0_RX

GT_CH0

GT_TRIG

PWM0_CH0

PWM0_TRIG

I2S_TX

SPI0_TX

UR0_TX

SCI1_TX

I2C1_RX

PWM1_CH1

PWM1_CH3

CH4

SPI1_RX

UR1_RX

SCI0_RX

I2C0_TX

UR1_TX

SCI0_TX

I2C1_TX

PWM1_CH2

PWM1_UEV

PWM1_CH0

PWM1_TRIG

AES_OUT

CH5

SPI1_TX

AES_IN

Channel Transfer

A PDMA channel transfer is split into multiple block transactions with PDMA arbitration occurring at the end of each block transaction. Although these channel transfers can all be activated, there is only one block transaction being transferred through the bus at a time. The channel transfer sequence depends upon the channel priority setting of each PDMA channel. The total transfer size is calculated from the block transaction count and block size. The block size is equal to the product of the block length and data bit width. For an efficient transfer, it is recommended that the block length is set as a multiple of 4.

The total transfer data size calculation is shown as the following equation:

A PDMA channel total transfer data size = Block transaction count × (Block length × Data width)

Channel Priority

The PDMA provides four priority levels, known as very high, high, medium and low, which can be configured by the application software. The PDMA also provides two methods to determine the channel priority. One is determined by application software configuration and the other is determined by the fixed hardware channel number. The PDMA arbitration processor will first check the software configuring channel priority level used to request the PDMA to provide the data transfer services. If more than one channel has the same priority, the channel with a smaller channel number will have priority over one with a larger channel number after arbitration.

Note that the highest priority channel will not occupy the PDMA service all the time when other lower priority channel requests are pending. The highest priority channel will be skipped for one block transaction time duration after one block transaction is complete. Then a block transaction requested by the second priority channel will be performed. After a block transaction of the second priority channel is complete, the PDMA arbitration processor will re-check all of the requested channel priority with the exception of the second priority channel since the second priority channel will be excluded after the end of a block transaction. Therefore, a block data transaction of the higher priority channel will be serviced and this channel will be excluded from the priority arbitration at the end of the block transaction. The PDMA will keep transferring the data using the method described above until all of the requested channel data transfer is complete. Refer to the accompanying figure for an example which shows the PDMA channel arbitration and scheduling.

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32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Channel 0: priority=very high, block count=2, block length=2

Channel 1: priority=high,

Channel 2: priority=low,

Priority: CH0 > CH1 > CH2 block count=3, block length=4 block count=3, block length=6

Priority: CH1 > CH2

Skip: CH0

Priority: CH1 > CH2

Skip: CH0

Priority: CH1

Skip: CH2

CH0

Block 0

CH1

Block 0

CH0

Block 1

CH1

Block 1

CH2

Block 0

CH1

Block 2

CH2

Block 1

Priority: CH0 > CH2

Skip: CH1

Priority: CH0 > CH1 > CH2

Skip: n/a

Priority: CH2

Skip: CH1

Figure 202. PDMA Channel Arbitration and Scheduling Example

Priority: CH2

Skip: n/a

Priority: CH2

Skip: n/a

CH2

Block 2

Time

Transfer Request

For a peripheral-to-memory or memory-to-peripheral transfer, one peripheral hardware request will trigger one block transaction of the dedicated PDMA channel. However, a complete data transfer of the relevant dedicated PDMA channel will be triggered when a software request occurs. It is recommended that the PDMA channel is configured to have a lower priority level and a smaller block length which is requested by the software for memory-to-memory data copy applications.

Address Mode

The PDMA provides three kinds of address modes which are the linear address, circular address and fixed address modes. These different address modes are used to support different kinds of source and destination address arrangements. The following table shows the detailed address mode combinations.

Table 75. PDMA Address Modes

Source Address Mode

Linear Increment / Decrement Address



Circular Increment / Decrement Address


Fixed Address

Fixed Address

Destination Address Mode



Fixed Address




Fixed Address

Linear Address Mode

After data is transferred, the current address will be increased or decreased by 1, 2 or 4 depending upon the data bit width setting.

Circular Address Mode

After data is transferred, the current address will be increased or decreased by 1, 2 or 4 depending upon the data bit width setting. When a block transaction is complete, the current address is loaded with the configured start address.

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Cortex ® -M0+ MCU

Fixed Address Mode

After data is transferred, the current address remains unchanged.

Auto-Reload

When the auto-reload control bit, AUTORLn, in the PDMA channel n control register

PDMACHnCR is set, both the channel n current address and the channel n current transfer size will be automatically reloaded with the corresponding start value after the current PDMA channel data transfer has totally completed. The channel n will still be activated and the next relative

PDMA request can be serviced without any re-configuration using the application software.

Transfer Interrupt

There are five transfer events during which the interrupts can be asserted for each PDMA channel.

These are the block transaction end (BE), half transfer (HT), transfer complete (TC), transfer error (TE) and global transfer event (GE). Setting the corresponding control bits in the PDMA interrupt enable register PDMAIER will enable the relevant interrupt events. The global interrupt event, GE, will be generated if any of the four interrupt events including the BE, HT, TC and TE occurs. Clearing the BE, HT, TC or TE event flag will also clear the GE flag. Clearing the GE flag will automatically clear all other event flags. The TE interrupt event will occur when the

PDMA accesses a system reserved address space or when the PDMA receives a request but the corresponding transfer size setting is equal to zero.

Register Map

The following table shows the PDMA registers and reset values.

Table 76. PDMA Register Map

Register Offset

PDMA Channel 0 Registers

PDMACH0CR 0x000

Description

PDMA Channel 0 Control Register

PDMACH0SADR 0x004

PDMACH0DADR 0x008

PDMACH0TSR 0x010

PDMACH0CTSR 0x014


PDMACH1CR 0x018

PDMA Channel 0 Source Address Register

PDMA Channel 0 Destination Address Register

PDMA Channel 0 Transfer Size Register

PDMA Channel 0 Current Transfer Size Register


PDMACH1SADR 0x01C PDMA Channel 1 Source Address Register

PDMACH1DADR 0x020 PDMA Channel 1 Destination Address Register

PDMACH1TSR 0x028 PDMA Channel 1 Transfer Size Register

PDMACH1CTSR 0x02C PDMA Channel 1 Current Transfer Size Register


PDMACH2CR 0x030

PDMACH2SADR 0x034



PDMACH2DADR

PDMACH2TSR

PDMACH2CTSR

0x038

0x040

0x044


PDMACH3CR 0x048



PDMA Channel 2 Current Transfer Size Register


Reset Value

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

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32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Register Offset Description


PDMACH3DADR 0x050

PDMACH3TSR 0x058





PDMACH4CR 0x060 PDMA Channel 4 Control Register

PDMACH4SADR 0x064

PDMACH4DADR 0x068

PDMACH4TSR 0x070




PDMACH4CTSR 0x074 PDMA Channel 4 Current Transfer Size Register


PDMACH5CR 0x078 PDMA Channel 5 Control Register


PDMACH5DADR 0x080

PDMACH5TSR 0x088




PDMA Global Register

PDMAISR 0x120

PDMAISCR 0x128

PDMAIER 0x130

PDMA Interrupt Status Register

PDMA Interrupt Status Clear Register

PDMA Interrupt Enable Register

Reset Value

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

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Cortex ® -M0+ MCU


PDMA Channel n Control Register – PDMACHnCR, n = 0 ~ 5

This register is used to specify the PDMA channel n data transfer configuration.

Offset: 0x000 (0), 0x018 (1), 0x030 (2), 0x048 (3), 0x060 (4), 0x078 (5)


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13

Reserved

12 11 10

AUTORLn FIXAENn

9 8

CHnPRI

Type/Reset

7 6 5 4

SRCAMODn SRCAINCn DSTAMODn DSTAINCn

RW 0 RW 0 RW 0 RW 0

3 2 1 0

DWIDTHn SWTRIGn CHnEN


Bits

[11]

[10]

[9:8]


AUTORLn Channel n Auto-Reload Enable Control

0: Disable Auto-Reload function

1: Enable Auto-Reload function

If this bit is set to 1 to enable the auto-reload function, both the channel n current address and the channel n current transfer size will be reloaded with the relevant start value and the PDMA channel n will still be activated when a transfer is complete. If this bit is cleared to 0, the channel n current address and the channel n current transfer size will remain unchanged and the PDMA channel n will be disabled after a transfer completion.

FIXAENn

CHnPRI

Channel n Fixed Address Enable control

0: Disable fixed address function in the circular address mode

1: Enable fixed address function in the circular address mode

Note that this bit is only available when the source or destination address mode is set to be in the circular address mode. For example, the source address mode is set as in the linear address mode and the destination address mode is set as in the circular mode. If this bit is set to enable the fixed address function, then the source address mode will still be in the linear address but the destination address mode will be in the fixed address mode instead of the circular address mode.

Channel n Priority

00: Low

01: Medium

10: High

11: Very high

The CHnPRI field is used to configure the channel priority using the application program. If there are more than one channel which have the same software configured priority level, the channel with the smaller channel number will have priority to transfer one block of data after the arbitration.

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32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Bits

[7]

[6]

[5]

[4]

[3:2]

[1]


SRCAMODn Channel n Source Address Mode selection

0: Linear address mode

1: Circular address mode

In the linear address mode, the current source address value can be increased or decreased, determined by the SRCAINCn bit value during a complete transfer.

In the circular address mode, the current source address value can be increased or decreased which is also determined by the SRCAINCn bit value during a block transfer and will be loaded with the lower 16-bit value of the PDMACHnSADR register, which will be regarded as the current source address when a block transaction has completed.

SRCAINCn Channel n Source Address Increment control

0: Increment

1: Decrement

This bit is used to determine whether the current source address is increased or decreased during a complete transfer in the linear address mode or a block transfer in the circular address mode.

DSTAMODn Channel n Destination Address Mode selection

0: Linear address mode

1: Circular address mode

In linear address mode, the current destination address value can be increased or decreased, determined by the DSTAINCn bit value during a complete transfer. In the circular address mode, the current destination address value can be increased or decreased which is also determined by the DSTAINCn bit value during a block transfer and will be loaded with the lower 16-bit value of the PDMACHnDADR register, which will be regarded as the current destination address when a block transfer has completed.

DSTAINCn Channel n Destination Address Increment Control

0: Increment

1: Decrement

This bit is used to determine if the current destination address is increased or decreased during a complete transfer in the linear address mode or a block transfer in the circular address mode.

DWIDTHn Data Bit Width selection

00: 8-bit

01: 16-bit

10: 32-bit

11: Reserved

The field is used to select the data bit width of the corresponding PDMA channel n.

SWTRIGn Software Trigger control

0: No operation

1: Software triggered transfer request

Setting this bit will generate a memory-to-memory software transfer request on the corresponding PDMA channel n. It is automatically cleared when a transfer has completely finished.

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HT32F5828

Cortex ® -M0+ MCU

Bits

[0]

Field

CHnEN

Descriptions

Channel n Enable control

0: Disable the PDMA channel n

1: Enable the PDMA channel n

Setting this bit will enable a software or hardware transfer request on the PDMA channel n. It is automatically cleared by hardware when a transfer has completed with the auto-reload function being disabled. However, if the AUTORLn bit is set to 1 to enable the auto-reload function, this bit will be remain high to enable the

PDMA channel n function for the next transfer request instead of automatically being cleared by hardware after a transfer has finished.

PDMA Channel n Source Address Register – PDMACHnSADR, n = 0 ~ 5

This register specifies the source address of the PDMA channel n.

Offset: 0x004 (0), 0x01C (1), 0x034 (2), 0x04C (3), 0x064 (4), 0x07C (5)


31 30 29 28 27

SADRn

26 25 24


23 22 21 20 19

SADRn

18 17 16


15 14 13 12 11

SADRn

10 9 8


7 6 5 4 3

SADRn

2 1 0


Bits

[31:0]

Field

SADRn

Descriptions

Channel n Source Address

The register is used to specify the 32-bit source address of the PDMA channel n.

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HT32F5828

Cortex ® -M0+ MCU

PDMA Channel n Destination Address Register – PDMACHnDADR, n = 0 ~ 5

This register specifies the destination address of the PDMA channel n.

Offset: 0x008 (0), 0x020 (1), 0x038 (2), 0x050 (3), 0x068 (4), 0x080 (5)


31 30 29 28 27

DADRn

26 25 24


23 22 21 20 19

DADRn

18 17 16


15 14 13 12 11

DADRn

10 9 8


7 6 5 4 3 2 1 0

DADRn


Bits

[31:0]

Field

DADRn

Descriptions

Channel n Destination Address

The register is used to specify the 32-bit destination address of the PDMA channel n.

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Cortex ® -M0+ MCU

PDMA Channel n Transfer Size Register – PDMACHnTSR, n = 0 ~ 5

This register is used to specify the block transaction count and block transaction length.

Offset: 0x010 (0), 0x028 (1), 0x040 (2), 0x058 (3), 0x070 (4), 0x088 (5)


31 30 29 28 27

BLKCNTn

26 25 24


23 22 21 20 19

BLKCNTn

18 17 16


15 14 13 12 11

Reserved

10 9 8

Type/Reset

7 6 5 4 3

BLKLENn

2 1 0


Bits

[31:16]

[7:0]


BLKCNTn Channel n Block Transaction Count

BLKCNTn represents the number of block transactions for a channel n complete transfer. The capacity of a complete transfer is the product of the BLKCNTn and

BLKLENn values. The maximum BLKCNTn value is 65,535.

BLKLENn Channel n Block Length

The BLKLENn represents the length of a data block. The data width is defined by the

DWIDTHn field in the PDMACHnCR register. The maximum BLKLENn value is 255.

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Cortex ® -M0+ MCU

PDMA Channel n Current Transfer Size Register – PDMACHnCTSR, n = 0 ~ 5

This register is used to indicate the current block transaction count.

Offset: 0x014 (0), 0x02C (1), 0x044 (2), 0x05C (3), 0x074 (4), 0x08C (5)


31 30 29 28 27

CBLKCNTn

26 25 24


23 22 21 20 19

CBLKCNTn

18 17 16


15 14 13 12 11

Reserved

10 9 8

Type/Reset

7 6 5 4 3

Reserved

2 1 0

Type/Reset

Bits

[31:16]


CBLKCNTn Channel n Current Block Count

The CBLKCNTn field is a 16-bit read-only value indicating the number of data blocks that remain to be transferred. After a data block has transferred completely, the

CBLKCNTn value will be decreased by 1. Writing a new value to the BLKCNTn field in the PDMACHnTSR register will update the CBLKCNTn field value.

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Cortex ® -M0+ MCU

PDMA Interrupt Status Register – PDMAISR

This register is used to indicate the corresponding interrupt status of the PDMA channel 0 ~ 5.

Offset: 0x120


Type/Reset

31 30 29 28 27 26 25 24

Reserved TEISTA5 TCISTA5 HTISTA5 BEISTA5 GEISTA5 TEISTA4

RO 0 RO 0 RO 0 RO 0 RO 0 RO 0

23 22 21 20 19 18 17 16

TCISTA4 HTISTA4 BEISTA4 GEISTA4 TEISTA3 TCISTA3 HTISTA3 BEISTA3


15 14 13 12 11 10 9 8

GEISTA3 TEISTA2 TCISTA2 HTISTA2 BEISTA2 GEISTA2 TEISTA1 TCISTA1


7 6 5 4 3 2 1 0

HTISTA1 BEISTA1 GEISTA1 TEISTA0 TCISTA0 HTISTA0 BEISTA0 GEISTA0


Bits

[29], [24],

[19], [14],

[9], [4]

Field

TEISTAn

[28], [23],

[18], [13],

[8], [3]

TCISTAn

[27], [22],

[17], [12],

[7], [2]

HTISTAn

[26], [21],

[16], [11],

[6], [1]

BEISTAn

Descriptions

Channel n Transfer Error Interrupt Status (n = 0 ~ 5)

0: No Transfer Error occurs

1: Transfer Error occurs

This bit is set by hardware and is cleared by writing a “1” into the corresponding interrupt status clear bit in the PDMAISCR register. A Transfer error will occur when the PDMA accesses a system reserved address space or when the PDMA receives a request but the corresponding transfer capacity is equal to zero.

Channel n Transfer Complete Interrupt Status (n = 0 ~ 5)

0: No Transfer Completion Occurs

1: Transfer Completion Occurs

This bit is set by hardware and is cleared by writing a “1” into the corresponding interrupt status clear bit in the PDMAISCR register. The Transfer Completion event will occur when the PDMA has completed a data transfer task.

Channel n Half Transfer Interrupt Status (n = 0 ~ 5)

0: No Half Transfer Event Occurs

1: Half Transfer Event Occurs

This bit is set by hardware and is cleared by writing a “1” into the corresponding interrupt status clear bit in the PDMAISCR register. A Half Transfer event will occur when the PDMA has completed half of the data transfer task.

Channel n Block Transaction End Interrupt Status (n = 0 ~ 5)

0: No Block Transaction End Event Occurs

1: Block Transaction End Event Occurs

This bit is set by hardware and is cleared by writing a “1” into the corresponding interrupt status clear bit in the PDMAISCR register. A Block Transaction End event will occur when the PDMA completes a data block transaction task.

Rev. 1.00 590 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Bits

[25], [20],

[15], [10],

[5], [0]

Field

GEISTAn

Descriptions

Channel n Global Transfer Interrupt Status (n = 0 ~ 5)

0: No TE, TC, HT or BE event occurs

1: TE, TC, HT, or BE event occurs

This bit is set by hardware and is cleared by writing a “1” into the corresponding interrupt status clear bit, GEICLRn, in the PDMAISCR register. A Global Transfer

Event will occur if any of the BE, HT, TC and TE events occurs. Also clearing any of the BE, HT, TC and TE event interrupt flags will clear the GE interrupt flag. Note that if a “1” is written into the GEICLRn bit in the PDMAISCR register to clear the GE interrupt flag, the BE, HT, TC and TE event interrupt flags will also be cleared to 0 together with the GE interrupt status flag.

PDMA Interrupt Status Clear Register – PDMAISCR

This register is used to clear the corresponding interrupt status bits in the PDMAISR Register.

Offset: 0x128


Type/Reset

31 30 29 28 27 26 25 24

Reserved TEICLR5 TCICLR5 HTICLR5 BEICLR5 GEICLR5 TEICLR4

WC 0 WC 0 WC 0 WC 0 WC 0 WC 0

23 22 21 20 19 18 17 16

TCICLR4 HTICLR4 BEICLR4 GEICLR4 TEICLR3 TCICLR3 HTICLR3 BEICLR3

Type/Reset WC 0 WC 0 WC 0 WC 0 WC 0 WC 0 WC 0 WC 0

15 14 13 12 11 10 9 8

GEICLR3 TEICLR2 TCICLR2 HTICLR2 BEICLR2 GEICLR2 TEICLR1 TCICLR1


7 6 5 4 3 2 1 0

HTICLR1 BEICLR1 GEICLR1 TEICLR0 TCICLR0 HTICLR0 BEICLR0 GEICLR0


Bits

[29], [24],

[19], [14],

[9], [4]

[28], [23],

[18], [13],

[8], [3]

[27], [22],

[17], [12],

[7], [2]

Field

TEICLRn

TCICLRn

Descriptions

Channel n Transfer Error Interrupt Status Clear (n = 0 ~ 5)

0: No Operation

1: Clear the corresponding TEISTAn bit in the PDMAISR register

Writing a “1” into the TEICLRn bit will clear the TEISTAn status bit in the PDMAISR register. This bit will be automatically cleared to 0 after a “1” is written.

Channel n Transfer Complete Interrupt Status Clear (n = 0 ~ 5)

0: No Operation

1: Clear the corresponding TCISTAn bit in the PDMAISR register

Writing a “1” into the TCICLRn bit will clear the TCISTAn status bit in the PDMAISR register. This bit will be automatically cleared to 0 after a “1” is written.

HTRICLRn Channel n Half Transfer Interrupt Status Clear (n = 0 ~ 5)

0: No Operation

1: Clear the corresponding HTISTAn bit in the PDMAISR register

Writing a “1” into the HTRICLRn bit will clear the HTISTAn status bit in the PDMAISR register. This bit will be automatically cleared to 0 after a “1” is written.

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Cortex ® -M0+ MCU

Bits

[26], [21],

[16], [11],

[6], [1]

Field

BEICLRn

[25], [20],

[15], [10],

[5], [0]

GEICLRn

Descriptions

Channel n Block Transaction End Interrupt Status Clear (n = 0 ~ 5)

0: No Operation

1: Clear the corresponding BEISTAn bit in the PDMAISR register

Writing a “1” into the BEICLRn bit will clear the BEISTAn status bit in the PDMAISR register. This bit will automatically cleared to 0 after a data “1” is written.

Channel n Global Transfer Event Interrupt Status Clear (n = 0 ~ 5)

0: No Operation

1: Clear the TEISTAn, TCISTAn, HTISTAn, BEISTAn and GEISTAn bits in the

PDMAISR register

Writing a “1” into the GEICLRn bit will clear the GEISTAn status bit together with the

TEISTAn, TCISTAn, HTISTAn and BEISTAn bits in the PDMAISR register. This bit will be automatically cleared to 0 after a “1” is written.

PDMA Interrupt Enable Register – PDMAIER

This register is used to enable or disable the related interrupts of the PDMA channel 0 ~ 5.

Offset: 0x130


Type/Reset

31

23

TCIE4

30

Reserved

22

HTIE4

29

TEIE5

21

BEIE4

28

TCIE5

20

GEIE4

27

HTIE5

19

TEIE3

26

BEIE5

18

TCIE3

25

GEIE5

17

HTIE3

24

TEIE4


16

BEIE3


15

GEIE3

14

TEIE2

13

TCIE2

12

HTIE2

11

BEIE2

10

GEIE2

9

TEIE1

8

TCIE1


7

HTIE1

6

BEIE1

5

GEIE1

4

TEIE0

3

TCIE0

2

HTIE0

1

BEIE0

0

GEIE0


Bits

[29], [24],

[19], [14],

[9], [4]

[28], [23],

[18], [13],

[8], [3]

[27], [22],

[17], [12],

[7], [2]

Field

TEIEn

TCIEn

HTIEn

Descriptions

Channel n Transfer Error Interrupt Enable control (n = 0 ~ 5)

0: Transfer Error interrupt is disabled

1: Transfer Error interrupt is enabled

This bit is set and cleared by software.

Channel n Transfer Complete Interrupt Enable control (n = 0 ~ 5)

0: Transfer Completion interrupt is disabled

1: Transfer Completion interrupt is enabled


Channel n Half Transfer Interrupt Enable control (n = 0 ~ 5)

0: Half Transfer interrupt is disabled

1: Half Transfer interrupt is enabled


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32-Bit Arm ®

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Cortex ® -M0+ MCU

Bits

[26], [21],

[16], [11],

[6], [1]

[25], [20],

[15], [10],

[5], [0]

Field

BEIEn

GEIEn

Descriptions

Channel n Block Transaction End Interrupt Enable control (n = 0 ~ 5)

0: Block Transaction End interrupt is disabled

1: Block Transaction End interrupt is enabled


Channel n Global Transfer Event Interrupt Enable control (n = 0 ~ 5)

0: Global Transfer Event interrupt is disabled

1: Global Transfer Event interrupt is enabled


Rev. 1.00 593 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

30

Divider (DIV)

Introduction

In order to enhance MCU performance, a divider is implemented within the device.

Features

▆

▆

Signed/unsigned 32-bit divider

Operation in 8 clock cycles, Load in 1 clock cycle

▆

Division by zero error flag


The division and modulus functions of the truncated division are related in the following way:

A / B = Q…R

Where “A” is Dividend, “B” is Divisor, “Q” is Quotient and “R” is Remainder. Divider requires a software trigger start signal by controlling the START bit in the CR register. The divider calculation complete flag will be set to 1 after 8 clock cycles, however, if the divisor register data is zero during the calculation, the division by zero error flag will be set to 1.

32-bit Divisor

32-bit Dividend

S/W Trigger

Figure 203. Divider Functional Diagram

32-bit / 32-bit

Divider

32-bit Quotient

32-bit Remainder

Division by Zero Error Flag

Calculation Complete Flag

Rev. 1.00 594 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Register Map

The following table shows the DIV registers and reset values.

Table 77. DIV Register Map

Register Offset

CR 0x000

DDR

DSR

0x004

0x008

QTR

RMR

0x00C

0x010

Description

Divider Control Register

Dividend Data Register

Divisor Data Register

Quotient Data Register

Remainder Data Register

Reset Value

0x0000_0008

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000


Divider Control Register – CR

This register contains the divider calculation complete flag, division by zero error flag and the calculation start control bit.

Offset: 0x000


31 30 29 28

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

21

13

5

Reserved

20

12

4

27

Reserved

19

Reserved

26

18

25

17

24

16

11

Reserved

10 9 8

3

COM

RO 1 RO

2

ZEF

0

1 0

Reserved START

RW 0

Bits

[3]

[2]

[0]

Field

COM

ZEF

START

Descriptions

Calculation Complete Flag

0: Data are invalid

1: New data are valid

When this bit is set to 1 by hardware, it indicates that the divider calculation is completed and data are valid. This bit is cleared to 0 by hardware after the calculation start.

Division By Zero Error Flag

0: Divisor is not zero

1: Divisor is zero

This bit is cleared to 0 by hardware after the calculation start.

Calculation Start Control Bit

0: No operation

1: Start the divider calculation

Writing 1 to this bit will start the divider calculation.

Rev. 1.00 595 of 637 December 28, 2020

32-Bit Arm ®

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Cortex ® -M0+ MCU

Dividend Data Register – DDR

The register contains the dividend of the divider.

Offset: 0x004


31 30 29 28 27

DDR

26 25 24


23 22 21 20 19

DDR

18 17 16


15 14 13 12 11

DDR

10 9 8


7 6 5 4 3 2 1 0

DDR


Bits

[31:0]

Field

DDR

Descriptions

This bit field is used to specify the dividend of the divider calculation.

Divisor Data Register – DSR

The register contains the divisor of the divider.

Offset: 0x008


31 30 29 28 27

DSR

26 25 24


23 22 21 20 19 18 17 16

DSR


15 14 13 12 11

DSR

10 9 8


7 6 5 4 3 2 1 0

DSR


Bits

[31:0]

Field

DSR

Descriptions

This bit field is used to specify the divisor of the divider calculation.

Rev. 1.00 596 of 637 December 28, 2020

32-Bit Arm ®

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Cortex ® -M0+ MCU

Quotient Data Register – QTR

The register contains the quotient of the divider calculation result.

Offset: 0x00C


31 30 29 28 27

QTR

26 25 24


23 22 21 20 19

QTR

18 17 16


15 14 13 12 11

QTR

10 9 8


7 6 5 4 3 2 1 0

QTR


Bits

[31:0]

Field

QTR

Descriptions

This bit field is used to store the queotient of the divider calculation result.

Remainder Data Register – RMR

The register contains the remainder of the divider calculation result.

Offset: 0x010


31 30 29 28 27

RMR

26 25 24


23 22 21 20 19 18 17 16

RMR


15 14 13 12 11

RMR

10 9 8


7 6 5 4 3 2 1 0

RMR


Bits

[31:0]

Field

RMR

Descriptions

This bit field is used to store the remainder of the divider calculation result.

Rev. 1.00 597 of 637 December 28, 2020

32-Bit Arm ®

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Cortex ® -M0+ MCU

31

Liquid Crystal Display Controller (LCD)

Introduction

The LCD controller is a digital controller/driver for monochrome passive liquid crystal displays with up to 8 common terminals and up to 37 segment terminals to drive 148 (4 commons × 37 segments) or 264 (8 commons × 33 segments) LCD picture elements (pixels). The exact number of terminals depends on the device pinout.

Each segment consists of a layer of liquid crystal molecules aligned between two electrodes. When a voltage greater than a threshold voltage is applied across the liquid crystal, the segment becomes visible.

An integrated charge pump function can be enabled to provide the LCD glass with higher voltage than the system voltage. The LCD display segment will degrade if the applied voltage has a DCcomponent. It is the average voltage generated by the LCD driver applied to the LCD segment that should be considered. If the applied root-mean-square (RMS) voltage is lower than the segment threshold voltage, the LCD segment will be clear, otherwise it will be dark.

APB Bus

CK_LSI

CK_LSE

CK_HSI

CK_HSE

LCDSRC[1:0]

LCDCPS[2:0]

÷ 1/2/4/8/16

( In CKCU IP)

CK_LCD

LCDPS[3:0]

PCLK_LCD

CK_LCD

PCLK_LCD

PCLK_LCD

Frequency Generator

16-bit prescaler

LCD Register LCDDIV[3:0]

MUX

CK_PS

Divide by 16 to 31

Interrupt

CK_DIV

COM0

LCD RAM

LCD Register

TYPE

STATIC

LCDPR

LCDEN

Pulse

Generator

HDEN

BIAS[1:0]

CPVS[2:0]

SEG

Driver

SEG[36:0]

37

READY

Contrast

Controller

Charge Pump

Resistor

Ladders

COM

Driver

COM[3:0]

COM[7:4]

COM3

SEG

COM

MUX

SEG[36:33]

4

SEG[32:0]

33

V

SS

1/3 ~ 1/4 V

LCD

2/3 ~ 3/4 V

LCD

1/2 V

LCD

V

LCD

SEG0

Analog

Switch

Array

SEG32

SEG33/

COM4

SEG34/

COM5

SEG35/

COM6

SEG36/

COM7

Figure 204. LCD Controller Block Diagram

Rev. 1.00 598 of 637 December 28, 2020

32-Bit Arm ®

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Cortex ® -M0+ MCU

Features

▆

▆

▆

▆

▆

▆

▆

▆

▆

▆

▆

LCD Driver function with Static, 1/2, 1/3, 1/4, 1/6 and 1/8 duty

LCD Driver function with Static, 1/2, 1/3 or 1/4 bias

Supports R type

LCD clock source can be selected from the LSI (32 kHz), LSE (32 kHz) or a clock ratio of the

HSI or HSE

Contains three embedded LCD bias reference resistor ladders

Double buffered memory

Software selectable charge pump voltage

The contrast can be adjusted using two different methods:

● When using the charge pump, the software can adjust the maximum output voltage VLCD

● Programmable dead time between frames – up to 7/2 phase periods for type A waveforms and

7 phase periods for type B waveforms

Software selectable waveform type: type A or type B waveform

LCD frame interrupt

Blink capability: Up to 1, 2, 3, 4, 6, 8 or all pixels which can be programmed to blink


Frequency Generator

The frequency generator can generate various LCD frame rates starting from an LCD input clock frequency, CK_LCD. The CK_LCD source can be chosen from the 32.768 kHz Low Speed

External RC (LSE), the 32 kHz Low Speed Internal RC (LSI) or a clock ratio of the HSI or HSE by configuring bits LCDSRC[1:0] in the GCFGR register in the CKCU IP. The LCDCPS[2:0] bits in the APBCFGR register in CKCU will select either the HSI or HSE divided by 1, 2 , 4, 8 or 16.

The input clock, CK_LCD, can be divided by any value from 1 to 2 15 × 31. The LCDPS[3:0] bits in the LCDFCR register, is used to select the CK_LCD divided ratio by 2 LCDPS[3:0] . The LCDDIV[3:0] bits in the LCDFCR register, can be used to divide the clock further by 16 to 31. The output of the frequency generator block is f

CK_DIV

which forms the time base for the entire LCD controller.

The output clock frequency f

CK_PS is: f

CK_PS

= f

CK_LCD

/ 2 LCDPS

And the relation between the frequency generator input clock frequency, f

CK_LCD clock frequency f

CK_DIV

is:

, and its output f

CK_DIV

= f

CK_LCD

/ [2 LCDPS × (16 + LCDDIV)]

The frame frequency, f frame

, is obtained by multiplying f

CK_DIV

with the duty: f frame

= f

CK_DIV

× duty

The frame frequency is often selected to be within a range of 30 Hz to 100 Hz. A dedicated blink prescaler selects the blink frequency. This frequency is defined as: f

BLINK

= f frame

/ 2 (BLINKF+3) , BLINKF[2:0] = 0, 1, 2, … , 7

Rev. 1.00 599 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Table 78. Frame Rate Calculation Example – CK_LCD 32 kHz, Frame Rate 30 Hz

CK_LCD

32768 Hz

32768 Hz

LCDPS

3

3 f

CK_PS

4096 Hz

4096 Hz

LCDDIV

1

6 f

CK_DIV

240.94 Hz

186.18 Hz

Duty

1/8

1/6 f frame

30.12 Hz

31.03 Hz

32768 Hz

32768 Hz

32768 Hz

32768 Hz

4

4

5

6

2048 Hz

2048 Hz

1024 Hz

512 Hz

1

6

1

1

120.47 Hz

93.09 Hz

60.24 Hz

30.12 Hz

1/4

1/3

1/2 static

30.12 Hz

31.03 Hz

30.12 Hz

30.12 Hz


CK_LCD LCDPS f

CK_PS

LCDDIV f

CK_DIV

Duty f frame

32768 Hz

32768 Hz

32768 Hz

2

2

3

8192 Hz

8192 Hz

4096 Hz

1

6

1

481.88 Hz

372.36 Hz

240.94 Hz

1/8

1/6

1/4

60.24 Hz

62.06 Hz

60.24 Hz

32768 Hz

32768 Hz

32768 Hz

3

4

5

4096 Hz

2048 Hz

1024 Hz

6

1

1

186.18 Hz

120.47 Hz

60.24 Hz

1/3

1/2 static

62.06 Hz

60.24 Hz

60.24 Hz


CK_LCD

32768 Hz

LCDPS

1 f

CK_PS

16384 Hz

LCDDIV

4 f

CK_DIV

819.20 Hz

Duty

1/8 f frame

102.40 Hz

32768 Hz

32768 Hz

32768 Hz

32768 Hz

32768 Hz

1

2

2

3

4

16384 Hz

8192 Hz

8192 Hz

4096 Hz

2048 Hz

11

4

11

4

4

606.80 Hz

409.60 Hz

303.41 Hz

204.80 Hz

102.40 Hz

1/6

1/4

1/3

1/2 static

101.14

102.40 Hz

101.14 Hz

102.40 Hz

102.40 Hz

Table 81. Frame Rate Calculation Example – CK_LCD 1 MHz, Frame Rate 30 Hz

CK_LCD

1 MHz

1 MHz

LCDPS

8

8 f

CK_PS

3906.25 Hz

3906.25 Hz

LCDDIV

0

5 f

CK_DIV

244.14 Hz

186.01 Hz

Duty

1/8

1/6 f frame

30.52 Hz

31.00 Hz

1 MHz

1 MHz

1 MHz

1 MHz

9

9

10

11

1953.13 Hz

1953.13 Hz

976.56 Hz

488.28 Hz

0

5

0

0

122.07 Hz

93.00 Hz

61.04 Hz

30.52 Hz

1/4

1/3

1/2 static

30.52 Hz

31.00 Hz

30.52 Hz

30.52 Hz

Table 82. Frame Rate Calculation Example – CK_LCD 1 MHz, Frame Rate 60 Hz

CK_LCD LCDPS f

CK_PS

LCDDIV f

CK_DIV

Duty f frame

1 MHz

1 MHz

1 MHz

7

7

8

7812.5 Hz

7812.5 Hz

3906.25 Hz

0

5

0

488.28 Hz

372.02 Hz

244.14 Hz

1/8

1/6

1/4

61.04 Hz

62.00 Hz

61.04 Hz

1 MHz

1 MHz

1 MHz

8

9

10

3906.25 Hz

1953.13 Hz

976.56 Hz

5

0

0

186.01 Hz

122.07 Hz

61.04 Hz

1/3

1/2 static

62.00 Hz

61.04 Hz

61.04 Hz

Rev. 1.00 600 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Table 83. Frame Rate Calculation Example – CK_LCD 1 MHz, frame rate 100 Hz

CK_LCD

1 MHz

1 MHz

LCDPS

6

6 f

CK_PS

15625 Hz

15625 Hz

LCDDIV

3

10 f

CK_DIV

822.37 Hz

600.96 Hz

Duty

1/8

1/6 f frame

102.80 Hz

100.16 Hz

1 MHz

1 MHz

1 MHz

1 MHz

7

7

8

9

7812.5 Hz

7812.5 Hz

3906.25 Hz

1953.13 Hz

3

10

3

3

411.18 Hz

300.48 Hz

205.59 Hz

102.80 Hz

1/4

1/3

1/2 static

102.80 Hz

100.16 Hz

102.80 Hz

102.80 Hz

Common and Segment Driver

The Common and Segment signals are generated by the common and segment driver block. LCDs can be driven by two types of waveforms, type A and type B. The LCD waveform type is selected by the TYPE bit in the LCDCR register. The Common signal has its max amplitude V is:

LCD

or V

SS only in the corresponding phase of a frame cycle, while during other phases, the signal amplitude

▆

▆

▆

1/2 V

LCD

for 1/2 bias

1/3 V

LCD

or 2/3 V

LCD

for 1/3 bias

1/4 V

LCD

or 3/4 V

LCD

for 1/4 bias

The bias mode can be selected to be 1/2, 1/3 or 1/4 using the BIAS bits in the LCDCR register.

The frame period in type A waveforms is equal to one odd or one even frame period in type B. The phase periods in type A and type B waveforms are equal (type A phase 0 = type B phase 0), and the phase period is equal to 1/ f

CK_DIV

:

Phase 0 = Phase 1 = Phase 2 = 1/ f

CK_DIV

Type A Waveforms

1 frame

Odd frame

Type B Waveforms

Even frame

1 frame

(odd frame)

COM

SEG

COM - SEG

V

LCD

2/3 V

LCD

1/3 V

LCD

V

SS

V

LCD

2/3 V

LCD

1/3 V

LCD

V

SS

V

LCD

2/3 V

LCD

1/3 V

LCD

V

SS

- 1/3 V

LCD

- 2/3 V

LCD

- V

LCD

Phase

0

Phase

1

Phase

2

Phase

0

Phase

1

Phase

2

Phase

0

Phase

1

Phase

2

Phase

0

Phase

1

Phase

2

Figure 205. Type A vs Type B Waveform – 1/3 Bias, 1/3 Duty

Rev. 1.00 601 of 637 December 28, 2020

32-Bit Arm ®

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Cortex ® -M0+ MCU

COM0

Depending upon the condition of the DTYC[2:0] bits in the LCDCR register, the COM signals are generated with a static duty, 1/2 duty, 1/3 duty, 1/4 duty, 1/6 duty or 1/8 duty. COM[n] (n = 0 to 7) is active during phase n in each frame. In type A waveforms, the COM pin is driven to V then to V and to V

SS

SS

within one phase. In type B waveforms, the COM pin is driven to V

LCD

in odd frames

in even frames.

LCD

and

When the LCDEN bit is cleared, all segment and common lines are pulled down to V

SS

.

COM0

SEG0

SEG1

COM0 - SEG0

COM0 - SEG1

V

LCD

V

SS

V

LCD

V

SS

V

LCD

V

SS

V

LCD

V

SS

- V

LCD

V

SS

Figure 206. Static Waveforms

Rev. 1.00 602 of 637 December 28, 2020

32-Bit Arm ®

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Cortex ® -M0+ MCU

COM1

COM0

COM0

COM1

SEG0

SEG1

COM0 - SEG0

(selected waveform)

COM0 – SEG1

(non-selected waveform)

Figure 207. 1/2 Duty, 1/2 Bias, Type A Waveforms

1 frame

V

LCD

1/2 V

LCD

V

SS

V

SS

V

LCD

1/2 V

LCD

V

SS

- 1/2 V

LCD

- V

LCD

V

LCD

1/2 V

LCD

V

SS

- 1/2 V

LCD

- V

LCD

V

LCD

1/2 V

LCD

V

SS

V

LCD

1/2 V

LCD

V

SS

V

LCD

1/2 V

LCD

Rev. 1.00 603 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

COM1

COM0

COM0

COM1

SEG0

SEG1

COM0 - SEG0

(selected waveform)

COM0 – SEG1



Rev. 1.00 604 of 637

1 frame

December 28, 2020

V

LCD

2/3 V

LCD

1/3 V

LCD

V

SS

V

LCD

2/3 V

LCD

1/3 V

LCD

V

SS

V

LCD

2/3 V

LCD

1/3 V

LCD

V

SS

V

LCD

2/3 V

LCD

1/3 V

LCD

V

SS

V

LCD

2/3 V

LCD

1/3 V

LCD

V

SS

- 1/3 V

LCD

- 2/3 V

LCD

- V

LCD

V

LCD

2/3 V

LCD

1/3 V

LCD

V

SS

- 1/3 V

LCD

- 2/3 V

LCD

- V

LCD

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

COM2

COM1

COM0

COM2

SEG0

COM0

COM1

SEG1

COM0 - SEG0


COM0 – SEG1

(selected waveform)


1 frame

Rev. 1.00 605 of 637 December 28, 2020

V

LCD

2/3 V

LCD

1/3 V

LCD

V

SS

V

LCD

2/3 V

LCD

1/3 V

LCD

V

SS

V

LCD

2/3 V

LCD

1/3 V

LCD

V

SS

V

LCD

2/3 V

LCD

1/3 V

LCD

V

SS

V

LCD

2/3 V

LCD

1/3 V

LCD

V

SS

V

LCD

2/3 V

LCD

1/3 V

LCD

V

SS

- 1/3 V

LCD

- 2/3 V

LCD

- V

LCD

V

LCD

2/3 V

LCD

1/3 V

LCD

V

SS

- 1/3 V

LCD

- 2/3 V

LCD

- V

LCD

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

COM2

COM1

COM0

COM3

COM0

COM1

COM2

COM3

SEG0

SEG1

COM0 – SEG0

(selected waveform)

COM0 – SEG1


1 frame


Rev. 1.00 606 of 637

V

LCD

2/3 V

LCD

1/3 V

LCD

V

SS

V

LCD

2/3 V

LCD

1/3 V

LCD

V

SS

V

LCD

2/3 V

LCD

1/3 V

LCD

V

SS

V

LCD

2/3 V

LCD

1/3 V

LCD

V

SS

- 1/3 V

LCD

- 2/3 V

LCD

- V

LCD

V

LCD

2/3 V

LCD

1/3 V

LCD

V

SS

- 1/3 V

LCD

- 2/3 V

LCD

- V

LCD

V

LCD

2/3 V

LCD

1/3 V

LCD

V

SS

V

LCD

2/3 V

LCD

1/3 V

LCD

V

SS

V

LCD

2/3 V

LCD

1/3 V

LCD

V

SS

December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

COM0

COM0

COM1

COM2

COM3

COM4

COM5

COM1

COM2

SEG0 SEG1

COM5

SEG0

COM0 – SEG0


COM1 – SEG0

(selected waveform)

1 frame

Figure 211. 1/6 Duty, 1/3 Bas, Type A Waveforms

Rev. 1.00 607 of 637

1/3 V

LCD

V

SS

- 1/3 V

LCD

- 2/3 V

LCD

- V

LCD

V

LCD

2/3 V

LCD

1/3 V

LCD

V

SS

- 1/3 V

LCD

- 2/3 V

LCD

- V

LCD

2/3 V

LCD

1/3 V

LCD

V

SS

V

LCD

2/3 V

LCD

1/3 V

LCD

V

SS

V

LCD

V

LCD

2/3 V

LCD

1/3 V

LCD

V

SS

V

LCD

2/3 V

LCD

1/3 V

LCD

V

SS

V

LCD

2/3 V

LCD

1/3 V

LCD

V

SS

V

LCD

2/3 V

LCD

December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

COM5

COM4

COM1

COM0

COM7

COM6

COM0

COM3

COM2 COM1

COM2

COM7

SEG0

COM0 – SEG0


COM1 – SEG0

(selected waveform)

1 frame


Rev. 1.00 608 of 637 December 28, 2020

V

LCD

2/3 V

LCD

1/3 V

LCD

V

SS

V

LCD

2/3 V

LCD

1/3 V

LCD

V

SS

V

LCD

2/3 V

LCD

1/3 V

LCD

V

SS

V

LCD

2/3 V

LCD

1/3 V

LCD

V

SS

V

LCD

2/3 V

LCD

1/3 V

LCD

V

SS

V

LCD

2/3 V

LCD

1/3 V

LCD

V

SS

-1/3 V

LCD

-2/3 V

LCD

-V

LCD

V

LCD

2/3 V

LCD

1/3 V

LCD

V

SS

-1/3 V

LCD

-2/3 V

LCD

-V

LCD

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

COM5

COM4

COM1

COM0

COM7

COM6

COM0

COM2

COM3

COM1

COM2

COM7

SEG0

COM0 – SEG0


COM1 – SEG0

(selected waveform)

1 frame


V

LCD

3/4 V

LCD

2/4 V

LCD

1/4 V

LCD

V

SS

V

LCD

3/4 V

LCD

2/4 V

LCD

1/4 V

LCD

V

SS

V

LCD

3/4 V

LCD

2/4 V

LCD

1/4 V

LCD

V

SS

V

LCD

3/4 V

LCD

2/4 V

LCD

1/4 V

LCD

V

SS

V

LCD

3/4 V

2/4 V

1/4 V

V

SS

LCD

LCD

LCD

V

LCD

3/4 V

LCD

2/4 V

LCD

1/4 V

LCD

V

SS

- 1/4 V

LCD

- 2/4 V

LCD

- 3/4 V

LCD

- V

LCD

V

LCD

3/4 V

LCD

2/4 V

LCD

1/4 V

LCD

V

SS

- 1/4 V

LCD

- 2/4 V

LCD

- 3/4 V

LCD

- V

LCD

Rev. 1.00 609 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

LCD Drive Selection

The LCD bias voltages are driven by the resistive networks. The resistive networks, one with low value resistor (R

L

) and one with high value resistor (R

H

) are respectively used to increase the current during transitions and reduce power consumption in the static state. If the LCDEN bit is set, the EN switch is closed. When clearing the LCDEN bit in type A waveforms, the EN switch is open at the end of the frame. In type B waveforms, the EN switch is open at the end of the even frame in order to avoid a medium voltage level different from 0.

HDEN EN

HRLEN

V

LCD

3 R

L

R

L

3 R

H

3/4 × V

LCD

R

H

2/3 × V

LCD

V

LCDR1

2 R

L

2 R

H

1/2 × V

LCD

V

LCDR2

2 R

L

R

L

3 R

L

2 R

H

1/3 × V

LCD

R

H

1/4 × V

LCD

3 R

H

V

LCDR3

BIAS[1]

/STATIC

Figure 214. LCD Voltage Control

V

SS

Rev. 1.00 610 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

High Drive Duration

The high drive duration bits, HDD[2:0], configure the time during which R

L

is enabled through the high drive enable switch, HDEN, when the levels of the common and segment lines change.

The low value resistor ladder can be reduced to half of its value by setting the half low resistor R

L enable bit, HRLEN. A short drive time will lead to lower power consumption but will also need a longer drive time to achieve the target contrast. In Figure 210, as the high drive duration HDD[2:0] is set to 3, the high drive duration is 3 × (1/f

CK_PS remaining time, HDEN is disabled by the hardware.

) during a single segment time. During the

▆

▆

▆

When HDEN=0, HDD[2:0]=0: HDEN switch is open and there is no high drive function.

When HDEN=0, HDD[2:0] have values other than 0, then the HDEN switch will be setup according to HDD[2:0] setup timing interval as shown below.

When HDEN=1, no matter what the value of HDD[2:0] is, the HDEN switch will always remain closed with the high drive function active.

Single Segment Time f

CK_PS

COUNT

HDD[2:0]

H00 H01 H02 H03 H04 H05 H06 H07

H3

High drive disable

(HDEN = 0)

High Drive

Duration

High drive enable

(HDEN = 1)

3/f

CK_PS

Figure 215. High Drive Duration

H00 H01

High drive enable

(HDEN = 1)

Dead Time

The LCD contrast can also be reduced by programming a dead time without modifying the frame rate. In the following figure, for type A waveforms, dead times are inserted between each frame.

For type B waveforms, dead times are inserted between the even and odd frames. During the dead time, the COM and SEG values are pulled down to V waveforms. The dead time duration is defined as follows:

SS

. The DEAD[2:0] bits can be used to program a time of up to 7/2 phase periods in type A waveforms and up to 7 periods in type B

Table 84. Dead Time Duration

DEAD[2:0]

Type A Waveforms

Phase Period Number b000 b001 b010 b011 b100 b101 b110 b111

0 1/2 2/2 3/2 4/2 5/2 6/2 7/2

Type B Waveforms

Phase Period Number

0 1 2 3 4 5 6 7

Rev. 1.00 611 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

1 frame

Type A Waveforms (DEAD[2:0] = 6)

Dead time

(3 phase periods)

COM

SEG

Odd frame

1 phase period 1/2 phase period

Type B Waveforms (DEAD[2:0] = 2)

Dead time

(2 phase periods)

Even frame

Odd frame

COM

SEG

1 phase period

Figure 216. Dead Time

V

LCD

2/3 V

LCD

1/3 V

LCD

V

SS

V

LCD

2/3 V

LCD

1/3 V

LCD

V

SS

Even frame

V

LCD

2/3 V

LCD

1/3 V

LCD

V

SS

V

LCD

2/3 V

LCD

1/3 V

LCD

V

SS

Rev. 1.00 612 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Double Buffer Memory

There are two levels of buffer memory. The first buffer level LCD RAM can be accessed by the application software through the APB interface. Once the LCD RAM is modified by the user program, the update display request flag, UDR, should be set to request the updated information to be moved to the second buffer level. This operation is implemented synchronously with the frame.

The LCD RAM is write-protected and the UDR flag will remain high until the update is completed.

Once the update is completed, the update display done flag, UDD, will be set and an interrupt will be generated if the UDDIE bit is set. The update will not occur (UDR = 1 and UDD = 0) until the display is enabled (LCDEN = 1).

LCD Low-power Modes

The LCD controller can be displayed in three power saving modes: Sleep, Deep-Sleep1,

Deep-Sleep2 modes. It can also be fully disabled to reduce the power consumption.

Table 85. LCD in Power Saving Modes

Mode

Sleep

Deep-Sleep1

Deep-Sleep2

Power-Down

LCD is active

LCD is active

LCD is active

LCD is inactive

Description

LCD Interrupts

There are two types of LCD interrupts: Start of Frame (SOF) and Update Display Done (UDD) interrupts. The SOF interrupt is executed if the SOFIE bit is set. The SOF flag is cleared by writing

1 to the SOFC bit. The LCD UDD interrupt is executed if the UDDIE bit is set. The UDD flag is cleared by writing 1 to the UDDC bit.

Table 86. LCD Interrupts

Interrupt Event

Start Of Frame – SOF

Update Display Done – UDD

Flag

SOF

UDD

Clearing Method Interrupt Enable Bit

Write SOFC = 1

Write UDDC = 1

SOFIE

UDDIE

Rev. 1.00 613 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Flowchart

START

Initialization

Enable AFIO, LCD clocks in CKCU

Configure LCD GPIO pins as alternate functions

Configure LCD controller according to the Display to be driven

Load the initial data to LCD RAM and set the UDR bit

Program desired frame rate (LCDPS[3:0] and LCDDIV[3:0])

Choose waveform type (TYPE bit)

Charge pump configuration (if charge pump is used)

Program charge pump voltage CPVS[2:0]

Set LCDPR bit

NO

Is charge pump ready?

(RDY = 1?)

YES

Enable the display (set LCDEN bit)

NO

Adjust contrast?

NO

Modify data?

NO

Change blink?

NO

Disable LCD

YES

Change LCDPS, LCDDIV, HDD, DEAD,HDEN or HRLEN

YES

YES

UDR=1?

NO

Modify the LCD RAM

Set UDR bit

YES

Change BLINK or BLINKF

YES

Disable the charge pump (clear LCDPR bit)

Disable the display (clear LCDEN)

NO

LCDENS = 0?

END

YES

Figure 217. Flowchart Example

Rev. 1.00 614 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Register Map

The following table shows the LCD registers and their reset values.

Table 87. LCD Register Map

Register

LCDCR

LCDFCR

LCDIER

LCDSR

LCDCLR

Offset

0x000

0x004

0x008

Description

LCD Control Register

LCD Frame Control Register

LCD Interrupt Enable Register

LCDRAM

0x00C

0x010

0x020

0x024

0x028

0x02C

0x030

0x034

0x038

0x03C

0x040

0x044

0x048

0x04C

0x050

0x054

0x058

0x05C

LCD Status Register

LCD Clear Register

LCD Display Memory COM0 (SEG31 to SEG0)
















Reset Value

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

Rev. 1.00 615 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU


LCD Control Register – LCDCR

This register specifies the LCD control and the enable bits.

Offset: 0x000


Type/Reset

31 30 29 28

Reserved

27 26 25 24

MMASK

RW 0

16 23 22 21 20 19

Reserved

18 17

Type/Reset

15

HRLEN

14

DSTAO

13 12 11 10 9 8

Reserved MUXCOM7 MUXCOM6 MUXCOM5 MUXCOM4


7

TYPE

6 5

BIAS

4

RW 0 RW 0 RW 0 RW 0

3

DTYC

2 1

LCDPR

0

LCDEN


Bits

[24]

[15]

[14]

[11]

[10]

[9]

[8]

Field

MMASK

Descriptions

MCONT Signal Mask Timing Selection

0: Mask time 25 ns

1: Mask time 40 ns

This bit controls the mask signal timing to mask the COM and SEG switch transient state.

HRLEN Half of R

L

Value Enable

0: Disable

1: Enable

The value of R

L

resistors are divided by 2 if HRLEN = 1.

DSTAO /STATIC Switch Control during Dead time

0: /STATIC switch is closed

1: /STATIC switch is open

This bit is used to control that the /STATIC switch is open or closed during the dead time duration.

MUXCOM7 Mux SEG[36] Enable

0: Mux SEG[36]/COM[7] is selected as COM[7]

1: Mux SEG[36]/COM[7] is selected as SEG[36]










Rev. 1.00 616 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Bits

[7]

[6:5]

[4:2]

[1]

[0]

Field

TYPE

BIAS

DTYC

LCDPR

LCDEN

Descriptions

Waveform Type Selection

0: Type A waveform

1: Type B waveform

Bias Selection

00: Bias 1/4

01: Bias 1/2

10: Bias 1/3

11: STATIC

These bits determine the bias used. When this field is set to value 11, the STATIC waveform is selected.

Duty Selection

000: Static duty

001: 1/2 duty

010: 1/3 duty

011: 1/4 duty

100: 1/6 duty

101: 1/8 duty

110: Reserved

111: Reserved

These bits determine the duty cycle. Values “110” and “111” are forbidden.

LCD Power Selection

0: External source VLCD pin – charge pump is disabled

1: Internal source – charge pump is enabled

The charge pump is enabled when this bit is set and is otherwise disabled when this bit is cleared.

LCD Controller Enable

0: LCD Controller disabled

1: LCD Controller enabled

This bit is set by software to enable the LCD Controller. If it is cleared by software to turn off the LCD, the LCD display will not stop immediately until the current frame is finished. When the LCD is disabled all COM and SEG pins are driven to V

SS

.

Rev. 1.00 617 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

LCD Frame Control Register – LCDFCR

This register specifies the LCD frame control bits.

Offset: 0x004


Type/Reset

31 30 29 28

Reserved

27 26 25 24

LCDPS

RW 0 RW 0

23 22

LCDPS

21 20 19

LCDDIV

18 17 16

BLINK


15 8

DEAD


7 6 5 4 3 2 1 0

DEAD

14

BLINKF

13

HDD

12

Type/Reset RW 0 RW 0 RW 0 RW 0

11

CPVS

10

Reserved

9

HDEN

RW 0

Bits

[25:22]

[21:18]

[17:16]

[15:13]

Field

LCDPS

LCDDIV

BLINK

BLINKF

Descriptions

LCD 16-bit Prescaler

0000: f

0001: f

0010: f

...

1111: f

CK_PS

CK_PS

CK_PS

CK_PS

= f

= f

= f

= f

CK_LCD

(do not support type A)

CK_LCD

CK_LCD

CK_LCD

/2

/4

/32768

These bits are written by software to define the division factor of the 16-bit prescaler.

LCD Clock Divider

0000: f

0001: f

0010: f

...

1111: f

CK_DIV

CK_DIV

CK_DIV

CK_DIV

= f

= f

= f

= f

CK_PS

/16

CK_PS

CK_PS

CK_PS

/17

/18

/31

These bits are written by software to define the division factor of the LCDDIV divider.

Blink Mode Selection

00: Blink is disabled

01: Blink is enabled on SEG[0], COM[0] – 1 pixel

10: Blink is enabled on SEG[0], all COMs – up to 8 pixels depending on the programmed duty

11: Blink is enabled on all SEGs and all COMs – all pixels

In the LCD RAM, the pixel will only blink if it is set to 1.

Blink Frequency Selection

000: f frame

/8

001: f frame

010: f frame

011: f frame

100: f frame

101: f frame

110: f frame

111: f frame

/16

/32

/64

/128

/256

/512

/1024

Rev. 1.00 618 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Bits

[12:10]

[9:7]

[6:4]

[0]

Field

CPVS

DEAD

HDD

HDEN

Descriptions

Charge Pump Voltage Selection

000: 2.65 V

001: 2.75 V

010: 2.85 V

011: 2.95 V

100: 3.10 V

101: 3.25 V

110: 3.40 V

111: 3.55 V

These bits specify one of the V

LCD

maximum voltages independent of V

DD

.

Dead Time Duration

In type A waveforms:

000: No dead time

001: 1/2 phase period dead time


......


In type B waveforms:

000: No dead time

001: 1 phase period dead time


......


These bits are written by software to configure the length of the dead time between frames. During the dead time the COM and SEG voltage levels are held at 0 V to reduce the contrast without modifying the frame rate.

High Drive Duration

000: 0

001: 1/f

010: 2/f

CK_PS

011: 3/f

100: 4/f

CK_PS

CK_PS

CK_PS

101: 5/f

110: 6/f

CK_PS

CK_PS

111: 7/f

CK_PS

These bits are written by software to define the high drive duration in terms of CK_

PS clock pulses. A short pulse will lead to lower power consumption, but displays with high internal resistance may need a longer pulse to achieve a satisfactory contrast. For type A waveforms, when the segment voltage needs to change it will be managed by the high drive.

High Drive Enable

0: Permanent high drive disabled

1: Permanent high drive enabled

This bit is written by software to enable a low resistance divider. Displays with high internal resistance may need a longer drive time to achieve a satisfactory contrast.

This bit is useful in cases where some additional power consumption can be tolerated.

Rev. 1.00 619 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

LCD Interrupt Enable Register – LCDIER

This register contains the corresponding LCD interrupt enable control bit.

Offset: 0x008


31 30 29

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

21

13

5

28

20

27

Reserved

19

Reserved

12

4

Reserved

11

Reserved

3

Type/Reset

Bits

[1]

[0]

Field

UDDIE

SOFIE

Descriptions

Update Display Done Interrupt Enable

0: LCD Update Display Done interrupt disable

1: LCD Update Display Done interrupt enable


Start of Frame Interrupt Enable

0: LCD Start of Frame interrupt disable

1: LCD Start of Frame interrupt enable


26

18

10

2

25

17

9

24

16

8

1

UDDIE

0

SOFIE

RW 0 RW 0

Rev. 1.00 620 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

LCD Status Register – LCDSR

This register contains the relevant LCD controller status.

Offset: 0x00C


31

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

30

22

29

21

28

20

27

Reserved

19

Reserved

26

18

25

17

24

16

14 13 12 11

Reserved

10 9 8

6 5

Reserved FCRSF

4

RDY

3

UDD

2

UDR

1

SOF

0

LCDENS

RO 0 RO 0 RO 0 RW 0 RO 0 RO 0

Bits

[5]

[4]

[3]

[2]

Field

FCRSF

RDY

UDD

UDR

Descriptions

LCD Frame Control Register Synchronization Flag

0: LCD Frame Control Register is not synchronised yet

1: LCD Frame Control Register is synchronised

This bit is set by hardware each time the LCDFCR register is updated in the

LCDCLK domain. It is cleared by hardware when writing to the LCDFCR register.

Ready Flag

0: Not ready

1: Charge pump is enabled and ready to provide the correct voltage

This bit indicates the status of the charge pump. It is set and cleared by hardware and only valid when the LCDPR bit is set high. When the LCDPR bit is set low, the

RDY bit will be kept low.

Update Display Done

0: No event

1: Update Display Request done. A UDD interrupt is generated if the UDDIE bit in the LCDIER register is set.

This bit is set by hardware. It is cleared by writing 1 to the UDDC bit in the LCDCLR register.

Update Display Request

0: No effect

1: Update Display request

Each time the software modifies the LCD RAM it must set the UDR bit to transfer the updated data to the second level buffer. The UDR bit remains set until the end of the update.

Note that before modifying the LCD RAM, it is necessary to read UDR to confirm that the hardware has cleared it to 0 before writing to the LCD RAM.

Rev. 1.00 621 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Bits

[1]

[0]

Field

SOF

LCDENS

Descriptions

Start of Frame Flag

0: No event

1: Start of Frame event occurred. An LCD Start of Frame Interrupt is generated if the SOFIE bit is set.

This bit is set by hardware at the beginning of a new frame at the same time as the display data is updated. It is cleared by writing 1 to the SOFC bit in the LCDCLR register.

LCD Enabled Status

0: LCD Controller is disabled

1: LCD Controller is enabled

This bit is set and cleared by hardware. This bit is set immediately when the LCDEN bit goes from 0 to 1. On deactivation this bit reflects the real status of the LCD so it becomes 0 at the end of the last displayed frame.

LCD Status Clear Register – LCDSCR

This register contains the LCD status clear bits.

Offset: 0x010


31 30 29 28 27

Reserved

Type/Reset

23 22 21 20 19

Reserved

Type/Reset

15 14 13 12 11

Reserved

Type/Reset

7 6 5 4

Reserved

3

Type/Reset

Bits

[1]

[0]

Field

UDDC

SOFC

26

18

10

25

17

9

24

16

8

2 1

UDDC

0

SOFC

WC 0 WC 0

Descriptions

Update Display Done Clear

0: No effect

1: Clear UDD flag

This bit is written by software to clear the UDD flag in the LCDSR register.

Start of Frame Flag Clear

0: No effect

1: Clear SOF flag

This bit is written by software to clear the SOF flag in the LCDSR register.

Rev. 1.00 622 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

LCD RAM – LCDRAM

This register contains pixels.

Offset: 0x020 ~ 0x05C


31 30 29 28 27

SEG_DATA

26 25 24


23 22 21 20 19

SEG_DATA

18 17 16


15 14 13 12 11

SEG_DATA

10 9 8


7 6 5 4 3 2 1 0

SEG_DATA


Bits

[31:0]


SEG_DATA SEG_DATA[31:0]

0: Pixel inactive

1: Pixel active

Each bit corresponds to one pixel of the LCD display.

Table 88. LCDRAM Register Map

Offset

0x20

0x24

0x28

Register

LCDRAM

(COM0)

LCDRAM

0x44

0x48

0x4C

0x50

0x54

0x58

0x5C

0x2C

0x30

0x34

0x38

0x3C

0x40

(COM1)

LCDRAM

(COM2)

LCDRAM

(COM3)

LCDRAM

(COM4)

LCDRAM

(COM5)

LCDRAM

(COM6)

LCDRAM

(COM7)

Bit[31:5]

SEG31 to SEG0

Reserved

SEG31 to SEG0

Reserved

SEG31 to SEG0

Reserved

SEG31 to SEG0

Reserved

SEG31 to SEG0

Reserved

SEG31 to SEG0

Reserved

SEG31 to SEG0

Reserved

SEG31 to SEG0

Reserved

Bit[4:0]

SEG36 to SEG32

SEG36 to SEG32

SEG36 to SEG32

SEG36 to SEG32

SEG36 to SEG32

SEG36 to SEG32

SEG36 to SEG32

SEG36 to SEG32

Rev. 1.00 623 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

32

AES Encrypt/Decrypt Interface (AES)

Introduction

The AES core supports both encryption and decryption functions and supports 128-bit input data.

It should be noted that hardware does not pad out any input data bit, therefore users need to do pad action by software at first.

AES

Cryp

Core

Module

AES Ctrl / Status / DMA / INT

Registers

Key Register

Initial Vector Register

AES Buffer

4 × 32 bits

Swap

Figure 218. AES Block Diagram

Features

▆

▆

▆

▆

▆

▆

▆

Supports AES Encrypt / Decrypt functions

Supports AES ECB/CBC/CTR modes

Supports Key Size of 128 bits

Supports 4 words Initial Vector for CBC and CTR modes

4 × 32 bits AES data buffer – each IN and OUT FIFO capacity

Supports Word Data Swap function

Supports PDMA Interface

AHB Bus

Rev. 1.00 624 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU


AES Mode Description

AES Electronic Codebook (AES-ECB) Mode

The 128-bit plaintext data comes from IN FIFO and will be sent to the AES core to do encryption operation after word swapping operation. The AES core uses a 128-bit key to process the encryption. After encryption, the AES core generates the ciphertext, which will be written into the

OUT FIFO after the word swapping operation.

IN FIFO

Plaintext

128

AES ECB

Encryption

SWAP

IN FIFO

Ciphertext

128

AES ECB

Decryption

SWAP

128

AES Core

Encryption

128

128

Key

128

AES Core

Decryption

128

128

Key

SWAP SWAP

128

OUT FIFO

Ciphertext

Figure 219. AES-ECB Mode

128

OUT FIFO

Plaintext

Rev. 1.00 625 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

AES Cipher Block Chaining (AES-CBC) Mode

During encryption in the CBC mode, each block of plaintext is XORed with the previous ciphertext block before being encrypted. The first initial vectors are initialized in the 1st encryption operation.

The plaintext after word swapping will be XORed with the initial vectors before encryption. When the encryption output data is pushed into the OUT FIFO, the initial vectors are updated by the encryption output data at the same time.

During decryption in the CBC mode, each block of plaintext is XORed with the previous ciphertext block after being decrypted. The first initial vectors are initialized in the 1st decryption operation.

The ciphertext after word swapping and decryption will be XORed with the initial vectors. When the XORed decryption output data is pushed into the OUT FIFO, the initial vectors are updated by the decryption input data at the same time for the next round ciphertext.

IN FIFO

Plaintext

128

AES CBC

Encryption

+

128

128

128

128

AES Core

Encryption

128

SWAP

IV0~3

Key

AHB Bus

SWAP

128

OUT FIFO

Ciphertext

Figure 220. AES-CBC Mode

When encryption output data is pushed into AES

Buffer, IV0~3 are updated by encryption output data at the same time

IN FIFO

Ciphertext

128

AES CBC

Decryption

128

AES Core

Decryption

128

+

128

128

128

SWAP

SWAP

Key

IV0~3

AHB Bus

128

OUT FIFO

Plaintext

When decryption output data is pushed into AES

Buffer, IV0~3 are updated by decryption input data at the same time

Rev. 1.00 626 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

AES Counter (AES-CTR) Mode

In the CTR mode, the initial vector counter value, after being increased by one, will be sent to the

AES core for encryption to generate ciphertext. The AES core uses the same AES direction setting in both encryption and decryption.

During encryption and decryption in the CTR mode, the IN FIFO data after word swapping is

XORed with the ciphertext. The XORed data is sent to the OUT FIFO after word swapping. The initial vector counter will be increased by one at the same time for the next round ciphertext.

SWAP

IN FIFO

Plaintext

128

AES CTR

Encryption

128

IV0~3

SWAP

AHB Bus

+1

+

128

128

128

AES Core

Encryption

128

OUT FIFO

Ciphertext

128

Key

When XORed output data is pushed into

AES buffer, IV0~3 are updated by IV0~3 + 1 at the same time

Figure 221. AES-CTR Mode

SWAP

IN FIFO

Ciphertext

128

AES CTR

Decryption

128

IV0~3

SWAP

AHB Bus

+1

128

+

128

128

AES Core

Decryption

128

128

Key

When XORed output data is pushed into

AES buffer, IV0~3 are updated by IV0~3 + 1 at the same time

OUT FIFO

Plaintext

AES Status

There are five status conditions in the AES for the user to monitor the AES situation. The

IFEMPTY bit will be set when the input FIFO is empty while the IFNFULL bit will be set when the input FIFO is not full. The OFNEMPTY bit will be set when there is data in the output FIFO.

The OFFULL bit will be set when the output FIFO is full. The BUSY bit will be set when the AES core is executing an encryption/decryption operation or the key is in expansion state.

AES PDMA Interface

The AES supports the 32 bits PDMA data transfer. When the IN FIFO is empty, the AES will send an IN FIFO request to the PDMA. When the OUT FIFO is full, the AES will send an OUT FIFO request to the PDMA.

Rev. 1.00 627 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

AES Interrupt

The IFINT request will be generated when the input FIFO is less than or equal to 1 AES block (4 ×

32 bits). The OFINT request will be generated when there is data in the AES buffer. When the

IFINT bit is set high, an AES interrupt will be generated if the IFINT interrupt is enabled and the

AES remains enabled. When the OFINT bit is set high, an AES interrupt can also be generated if the OFINT interrupt is enabled irrespective of the AES enable/disable condition.

AES_EN

IFINT

IFINTEN

OFINT

OFINTEN

Figure 222. AES Interrupt

AES_INT

AES Initial Vector

The initial vectors (IV0 ~ 3) are not used in the ECB mode. The initial vectors are initialized in the first block of AES input data in the CBC and CTR modes. After the first AES block of input data, the values of the initial vectors will be updated by hardware automatically for the next block of

AES input data. The initial vectors in the CTR mode contain nonce, initial vector and counter. The counter will be increased by 1 after every AES data block action.

Nonce ( 32 bits )

Initial Vector

( 64 bits )

Counter ( 32 bits )

IV0

IV1, 2

IV3

Figure 223. Initial Vector for CTR Mode

Rev. 1.00 628 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

AES Word Swap

The AES supports a word swap function. The swap action is performed between IN FIFO and

AES block data, it is also executed between the AES block data and OUT FIFO. If the word swap function is required, the SWAP bit in the AESCR register should be set high.

31 0

.

.

.

Word 3

Word 2

Word 1

Word 0

31 0

Word 0

Word 1

Word 2

Word 3

.

.

.

AES Block Data

SWAP = 0

127 96

Word 0

95 64

Word 1

63 32

Word 2

31 0

Word 3

Word 2 Word 1 Word 0 SWAP = 1

Figure 224. AES Word Swap Function

Word 3

Register Map

The following table shows the AES registers and reset values.

Table 89. AES Register Map

Register Offset

AESCR 0x000 AES Control Register

Description

AESSR

AESDMAR

AESISR

AESIER

0x004

0x008

0x00C

0x010

AESDINR 0x014

AESDOUTR 0x018

AESKEYR0 0x01C

AESKEYR1 0x020

AESKEYR2 0x024

AESKEYR3 0x028

AESIVR0

AESIVR1

AESIVR2

AESIVR3

0x03C

0x040

0x044

0x048

AES Status Register

AES DMA Register

AES Interrupt Status Register

AES Interrupt Enable Register

AES Data Input Register

AES Data Output Register

AES Key Register 0

AES Key Register 1

AES Key Register 2

AES Key Register 3

AES Initial Vector Register 0




Reset Value

0x0000_0200

0x0000_0003

0x0000_0000

0x0000_0001

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

Rev. 1.00 629 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU


AES Control Register – AESCR

This register specifies the AES control setting.

Offset: 0x000


31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

Type/Reset

Type/Reset

15

7

Reserved

14 13

Reserved

12 11 10

FFLUSH

9

ENDIAN

8

SWAP

6 5 4

KEYSIZE KEYSTART

3

RW 0 RW 1 RW 0

2

MODE

1

DIR

0

AESEN

RO 0 RO 0 RW 0 RW 0 RW 0 RW 0 RW 0

Bits

[10]

[9]

[8]

[6:5]

[4]

[3:2]

[1]

[0]

Field

FFLUSH

ENDIAN

Descriptions

AES IN/OUT FIFO Flush

0: No action

1: Flush FIFO

The bit is cleared to 0 by hardware automatically. The bit can be set only in the AES disable state.

Endian Selection

0: Big-endian

1: Little-endian

This setting will apply to IN/OUT FIFO data, KEY and IV.

SWAP AES Data Swap Function

0: No Swap

1: Word Swap

This setting will apply to IN/OUT FIFO data.

KEYSIZE AES Key Size

00: 128 bits

Others: Reserved

KEYSTART AES Key Start

0: Key doesn’t Start

1: Key Start

It is cleared to 0 by hardware automatically. The bit works when in the AES enable state.

MODE

DIR

AESEN

AES Function Mode

00: ECB mode

01: CBC mode

1x: CTR mode

AES Direction

0: Encryption

1: Decryption

AES Enable

0: AES is disabled

1: AES is enabled

Rev. 1.00 630 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

AES Status Register – AESSR

This register specifies the AES status.

Offset: 0x004


31 30 29

Type/Reset

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

Reserved

21

13

5

28

20

27

Reserved

19

Reserved

26

18

25

17

24

16

12 11

Reserved

10 9 8

4

BUSY

3 2 1 0

OFFULL OFNEMPTY IFNFULL IFEMPTY

RO 0 RO 0 RO 0 RO 1 RO 1

Bits

[4]

[3]

[2]

[1]

[0]

Field

BUSY

OFFULL

Descriptions

Busy bit

0: AES is not busy

1: AES is busy

AES is busy when AES is executing the encryption/decryption operation or the key is in expansion state.

Output FIFO is Full

0: Output FIFO is not full

1: Output FIFO is full

OFNEMPTY Output FIFO is not Empty

0: Output FIFO is empty

1: Output FIFO is not empty

IFNFULL Input FIFO is not Full

0: Input FIFO is full

1: Input FIFO is not full

IFEMPTY Input FIFO is Empty

0: Input FIFO is not empty

1: Input FIFO is empty

Rev. 1.00 631 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

AES DMA Register – AESDMAR

This register specifies the DMA setting.

Offset: 0x008


31 30 29

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

21

13

5

28

20

27

Reserved

19

Reserved

12

4

Reserved

11

Reserved

3

Type/Reset

Bits

[1]

[0]


OFDMAEN Output FIFO DMA Enable

0: DMA is disabled

1: DMA is enabled

IFDMAEN Input FIFO DMA Enable

0: DMA is disabled

1: DMA is enabled

26

18

10

25

17

9

24

16

8

2 1 0

OFDMAEN IFDMAEN

RW 0 RW 0

Rev. 1.00 632 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

AES Interrupt Status Register – AESISR

The register specifies the interrupt status setting.

Offset: 0x00C


31 30 29

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

21

13

5

28

20

27

Reserved

19

Reserved

12

4

Reserved

11

Reserved

3

Type/Reset

Bits

[1]

[0]

Field

OFINT

IFINT

Descriptions

Output FIFO Interrupt Status

0: No Output FIFO Interrupt

1: Output FIFO Interrupt

Input FIFO interrupt Status

0: No Input FIFO Interrupt

1: Input FIFO Interrupt

26

18

10

25

17

9

24

16

8

2 1

OFINT

0

IFINT

RO 0 RO 1

Rev. 1.00 633 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

AES Interrupt Enable Register – AESIER

The register specifies the interrupt enable setting.

Offset: 0x010


31 30 29

Type/Reset

Type/Reset

Type/Reset

23

15

7

22

14

6

21

13

5

28

20

27

Reserved

19

Reserved

12

4

Reserved

11

Reserved

3

Type/Reset

Bits

[1]

[0]

Field

OFINTEN

IFINTEN

Descriptions

Output FIFO Interrupt Enable bit

0: Interrupt is disabled

1: Interrupt is enabled

Input FIFO Interrupt Enable bit

0: Interrupt is disabled

1: Interrupt is enabled

26

18

10

25

17

9

24

16

8

2 1 0

OFINTEN IFINTEN

RW 0 RW 0

Rev. 1.00 634 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

AES DATA Input Register – AESDINR

The register specifies the data input setting.

Offset: 0x014


31 30 29 28 27

DIN

26 25 24


23 22 21 20 19

DIN

18 17 16


15 14 13 12 11

DIN

10 9 8


7 6 5 4 3 2 1 0

DIN


Bits

[31:0]

Field

DIN

Descriptions

AES DATA Input

0x0000_0000 ~ 0xFFFF_FFFF

AES DATA Output Register – AESDOUTR

The register specifies the data output setting.

Offset: 0x018


31 30 29 28 27

DOUT

26 25 24


23 22 21 20 19 18 17 16

DOUT


15 14 13 12 11

DOUT

10 9 8


7 6 5 4 3 2 1 0

DOUT


Bits

[31:0]

Field

DOUT

Descriptions

AES Data Output


Rev. 1.00 635 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

AES Key Register n – AESKEYRn, n = 0 ~ 3

The register specifies the data of Key data n.

Offset: 0x01C ~ 0x028


31 30 29 28 27

KeyData

26 25 24


23 22 21 20 19

KeyData

18 17 16


15 14 13 12 11

KeyData

10 9 8


7 6 5 4 3 2 1 0

KeyData


Bits

[31:0]

Field

KeyData

Descriptions

KeyData


AES Initial Vector Register n – AESIVRn, n = 0 ~ 3

The register specifies the data of Initial Vector data n.

Offset: 0x03C ~ 0x048


31 30 29 28 27

IVData

26 25 24


23 22 21 20 19 18 17 16

IVData


15 14 13 12 11

IVData

10 9 8


7 6 5 4 3 2 1 0

IVData


Bits

[31:0]

Field

IVData

Descriptions

Initial Vector Data


Rev. 1.00 636 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Copyright

©

2020 by HOLTEK SEMICONDUCTOR INC.

The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek's products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.

holtek.com.

Rev. 1.00 637 of 637 December 28, 2020