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637
32-Bit Arm ®
HT32F5828
Cortex ® -M0+ MCU
Flash Memory Architecture
The Flash memory consists of up to 128 KB main Flash Block with 1 KB per page and 2 KB
Information Block for Boot Loader. The main Flash memory contains a total of 128 pages (or 64 pages for 64 KB device and so on) which can be erased individually. The following table shows the base address, size, and protection setting bit of each page.
Table 4. Flash Memory and Option Byte
Block Name Address
Page 0
Page 1
Page 2
Page 3
0x0000_0000 ~ 0x0000_03FF
0x0000_0400 ~ 0x0000_07FF
0x0000_0800 ~ 0x0000_0BFF
0x0000_0C00 ~ 0x0000_0FFF
Main Flash
Block
:
:
Page 124
:
:
0x0001_F000 ~ 0x0001_F3FF
Page 125
Page 126
0x0001_F400 ~ 0x0001_F7FF
0x0001_F800 ~ 0x0001_FBFF
Page 127
(Option Byte)
Physical address:
0x0001_FC00 ~ 0x0001_FFFF
Alias address:
0x1FF0_0000 ~ 0x1FF0_03FF
Information Block Boot Loader 0x1F00_0000 ~ 0x1F00_07FF
Page
Protection Bit Size
OB_PP [0]
OB_PP [1]
OB_PP [2]
OB_PP [3]
:
:
OB_PP [124]
OB_PP [125]
OB_PP [126]
OB_CP [1]
1 KB
1 KB
1 KB
1 KB
:
:
1 KB
1 KB
1 KB
1 KB
NA 2 KB
Notes: 1. The Information Block stores the boot loader and this block can not be programmed or erased by users.
2. The Option Byte is always located at the last page of the Main Flash Block.
Wait State Setting
When the CPU clock, HCLK, is faster than the Flash memory access speed, the wait state cycles must be inserted during CPU fetching instructions or loading data from the Flash memory. The wait state can be changed by setting the WAIT [2:0] field of the Flash Pre-fetch Control Register,
CFCR. In order to meet the wait state requirement, the following two rules should be considered.
▆
▆
The HCLK clock is switched from low to high frequency:
Change the wait state setting first and then switch the HCLK clock.
The HCLK clock is switched from high to low frequency:
Switch the HCLK clock first and then change the wait state setting.
The following table shows the relationship between the wait state cycle and HCLK. The default wait state is 0 since the High Speed Internal oscillator, HSI, which operates at a frequency of 8
MHz is selected as the HCLK clock source after a system reset.
Table 5. Relationship between Wait State Cycle and HCLK
Wait State Cycle
0
1
2
HCLK
0 MHz < HCLK ≤ 20 MHz
20 MHz < HCLK ≤ 40 MHz
40 MHz < HCLK ≤ 60 MHz
Rev. 1.00 45 of 637 December 28, 2020
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Table of contents
- 28 1 Introduction
- 28 Overview
- 28 Features
- 33 Device Information
- 34 Block Diagram
- 35 2 Document Conventions
- 36 3 System Architecture
- 36 -M0+ Processor
- 37 Bus Architecture
- 38 Memory Organization
- 39 Memory Map
- 41 Embedded Flash Memory
- 41 Embedded SRAM Memory
- 41 AHB Peripherals
- 42 APB Peripherals
- 43 4 Flash Memory Controller (FMC)
- 43 Introduction
- 43 Features
- 44 Functional Descriptions
- 44 Flash Memory Map
- 45 Flash Memory Architecture
- 45 Wait State Setting
- 46 Page Erase
- 48 Mass Erase
- 49 Word Programming
- 50 Option Byte Description
- 51 Page Erase/Program Protection
- 52 Security Protection
- 53 Register Map
- 54 Register Descriptions
- 54 Flash Target Address Register – TADR
- 55 Flash Write Data Register – WRDR
- 56 Flash Operation Command Register – OCMR
- 57 Flash Operation Control Register – OPCR
- 58 Flash Operation Interrupt Enable Register – OIER
- 59 Flash Operation Interrupt and Status Register – OISR
- 61 Flash Page Erase/Program Protection Status Register – PPSR
- 62 Flash Security Protection Status Register – CPSR
- 57 December
- 63 Flash Vector Mapping Control Register – VMCR
- 64 Flash Manufacturer and Device ID Register – MDID
- 65 Flash Page Number Status Register – PNSR
- 66 Flash Page Size Status Register – PSSR
- 66 Device ID Register – DID
- 67 Flash Pre-fetch Control Register – CFCR
- 68 Custom ID Register n – CIDRn (n = 0 ~ 3)
- 69 5 Reset Control Unit (RSTCU)
- 69 Introduction
- 69 Functional Descriptions
- 69 Power-On Reset
- 70 System Reset
- 70 AHB and APB Unit Reset
- 70 Register Map
- 71 Register Descriptions
- 71 Global Reset Status Register – GRSR
- 72 AHB Peripheral Reset Register – AHBPRSTR
- 73 APB Peripheral Reset Register 0 – APBPRSTR
- 75 APB Peripheral Reset Register 1 – APBPRSTR
- 77 6 Clock Control Unit (CKCU)
- 77 Introduction
- 79 Features
- 79 Functional Descriptions
- 79 High Speed External Crystal Oscillator – HSE
- 80 High Speed Internal RC Oscillator – HSI
- 80 Auto Trimming of High Speed Internal RC Oscillator – HSI
- 82 Phase Locked Loop – PLL
- 83 USB Phase Locked Loop – USB PLL
- 85 Low Speed External Crystal Oscillator – LSE
- 85 Low Speed Internal RC Oscillator – LSI
- 85 Clock Ready Flag
- 85 System Clock (CK_SYS) Selection
- 86 HSE Clock Monitor
- 86 Clock Output Capability
- 87 Register Map
- 88 Register Descriptions
- 89 Global Clock Control Register – GCCR
- 91 Global Clock Status Register – GCSR
- 92 Global Clock Interrupt Register – GCIR
- 94 PLL Control Register – PLLCR
- 88 December
- 136 EXTI Interrupt Wakeup Control Register – EXTIWAKUPCR
- 137 EXTI Interrupt Wakeup Polarity Register – EXTIWAKUPPOLR
- 138 EXTI Interrupt Wakeup Flag Register – EXTIWAKUPFLG
- 139 9 General Purpose I/O (GPIO)
- 139 Introduction
- 140 Features
- 140 Functional Descriptions
- 140 General Purpose I/O – GPIO
- 142 GPIO Locking Mechanism
- 142 Register Map
- 144 Register Descriptions
- 144 Port A Data Direction Control Register – PADIRCR
- 145 Port A Input Function Enable Control Register – PAINER
- 146 Port A Pull-Up Selection Register – PAPUR
- 147 Port A Pull-Down Selection Register – PAPDR
- 148 Port A Open-Drain Selection Register – PAODR
- 149 Port A Drive Current Selection Register – PADRVR
- 150 Port A Lock Register – PALOCKR
- 151 Port A Data Input Register – PADINR
- 151 Port A Output Data Register – PADOUTR
- 152 Port A Output Set/Reset Control Register – PASRR
- 153 Port A Output Reset Register – PARR
- 153 Port B Data Direction Control Register – PBDIRCR
- 154 Port B Input Function Enable Control Register – PBINER
- 155 Port B Pull-Up Selection Register – PBPUR
- 156 Port B Pull-Down Selection Register – PBPDR
- 157 Port B Open-Drain Selection Register – PBODR
- 158 Port B Drive Current Selection Register – PBDRVR
- 159 Port B Lock Register – PBLOCKR
- 160 Port B Data Input Register – PBDINR
- 160 Port B Output Data Register – PBDOUTR
- 161 Port B Output Set/Reset Control Register – PBSRR
- 162 Port B Output Reset Register – PBRR
- 162 Port C Data Direction Control Register – PCDIRCR
- 163 Port C Input Function Enable Control Register – PCINER
- 164 Port C Pull-Up Selection Register – PCPUR
- 165 Port C Pull-Down Selection Register – PCPDR
- 166 Port C Open-Drain Selection Register – PCODR
- 167 Port C Drive Current Selection Register – PCDRVR
- 168 Port C Lock Register – PCLOCKR
- 169 Port C Data Input Register – PCDINR
- 169 Port C Output Data Register – PCDOUTR
- 170 Port C Output Set/Reset Control Register – PCSRR
- 167 December
- 171 Port C Output Reset Register – PCRR
- 172 Port D Data Direction Control Register – PDDIRCR
- 173 Port D Input Function Enable Control Register – PDINER
- 174 Port D Pull-Up Selection Register – PDPUR
- 175 Port D Pull-Down Selection Register – PDPDR
- 176 Port D Open-Drain Selection Register – PDODR
- 177 Port D Drive Current Selection Register – PDDRVR
- 178 Port D Lock Register – PDLOCKR
- 179 Port D Data Input Register – PDDINR
- 180 Port D Output Data Register – PDDOUTR
- 181 Port D Output Set/Reset Control Register – PDSRR
- 182 Port D Output Reset Register – PDRR
- 183 Port E Data Direction Control Register – PEDIRCR
- 184 Port E Input Function Enable Control Register – PEINER
- 185 Port E Pull-Up Selection Register – PEPUR
- 186 Port E Pull-Down Selection Register – PEPDR
- 187 Port E Open-Drain Selection Register – PEODR
- 188 Port E Drive Current Selection Register – PEDRVR
- 189 Port E Lock Register – PELOCKR
- 190 Port E Data Input Register – PEDINR
- 191 Port E Output Data Register – PEDOUTR
- 192 Port E Output Set/Reset Control Register – PESRR
- 193 Port E Output Reset Register – PERR
- 194 10 Alternate Function Input/Output Control Unit (AFIO)
- 194 Introduction
- 195 Features
- 195 Functional Descriptions
- 195 External Interrupt Pin Selection
- 196 Alternate Function
- 196 Lock Mechanism
- 196 Register Map
- 197 Register Descriptions
- 197 EXTI Source Selection Register 0 – ESSR
- 198 EXTI Source Selection Register 1 – ESSR
- 201 11 Nested Vectored Interrupt Controller (NVIC)
- 201 Introduction
- 202 Features
- 203 Functional Descriptions
- 203 SysTick Calibration
- 203 Register Map
- 201 December
- 237 General Call Addressing
- 237 Bus Error
- 238 Address Mask Enable
- 238 Address Snoop
- 238 Operation Mode
- 242 Conditions of Holding SCL Line
- 243 C Timeout Function
- 243 PDMA Interface
- 244 Register Map
- 244 Register Descriptions
- 244 C Control Register – I2CCR
- 246 C Interrupt Enable Register – I2CIER
- 247 C Address Register – I2CADDR
- 248 C Status Register – I2CSR
- 251 C SCL High Period Generation Register – I2CSHPGR
- 252 C SCL Low Period Generation Register – I2CSLPGR
- 253 C Data Register – I2CDR
- 254 C Target Register – I2CTAR
- 255 C Address Mask Register – I2CADDMR
- 256 C Address Snoop Register – I2CADDSR
- 257 C Timeout Register – I2CTOUT
- 258 14 Serial Peripheral Interface (SPI)
- 258 Introduction
- 259 Features
- 259 Functional Descriptions
- 259 Master Mode
- 259 Slave Mode
- 259 SPI Serial Frame Format
- 264 SPI Dual Mode
- 266 Status Flags
- 269 PDMA Interface
- 269 Register Map
- 270 Register Descriptions
- 270 SPI Control Register 0 – SPICR
- 272 SPI Control Register 1 – SPICR
- 274 SPI Interrupt Enable Register – SPIIER
- 275 SPI Clock Prescaler Register – SPICPR
- 275 SPI Data Register – SPIDR
- 276 SPI Status Register – SPISR
- 277 SPI FIFO Control Register – SPIFCR
- 278 SPI FIFO Status Register – SPIFSR
- 279 SPI FIFO Time Out Counter Register – SPIFTOCR
- 275 December
- 280 15 Universal Synchronous Asynchronous Receiver Transmitter (USART)
- 280 Introduction
- 281 Features
- 281 Functional Descriptions
- 281 Serial Data Format
- 282 Baud Rate Generation
- 284 Hardware Flow Control
- 287 RS485 Mode
- 289 Synchronous Master Mode
- 291 Interrupts and Status
- 291 PDMA Interface
- 291 Register Map
- 292 Register Descriptions
- 292 USART Data Register – USRDR
- 293 USART Control Register – USRCR
- 295 USART FIFO Control Register – USRFCR
- 296 USART Interrupt Enable Register – USRIER
- 298 USART Status & Interrupt Flag Register – USRSIFR
- 300 USART Timing Parameter Register – USRTPR
- 301 USART IrDA Control Register – IrDACR
- 302 USART RS485 Control Register – RS485CR
- 303 USART Synchronous Control Register – SYNCR
- 304 USART Divider Latch Register – USRDLR
- 305 USART Test Register – USRTSTR
- 306 16 Universal Asynchronous Receiver Transmitter (UART)
- 306 Introduction
- 307 Features
- 307 Functional Descriptions
- 307 Serial Data Format
- 308 Baud Rate Generation
- 309 Interrupts and Status
- 309 PDMA Interface
- 310 Register Map
- 310 Register Descriptions
- 310 UART Data Register – URDR
- 311 UART Control Register – URCR
- 312 UART Interrupt Enable Register – URIER
- 314 UART Status & Interrupt Flag Register – URSIFR
- 315 UART Divider Latch Register – URDLR
- 316 UART Test Register – URTSTR
- 311 December
- 317 17 Smart Card Interface (SCI)
- 317 Introduction
- 318 Features
- 318 Functional Descriptions
- 318 Elementary Time Unit Counter
- 320 Guard Time Counter
- 321 Waiting Time Counter
- 322 Card Clock and Data Selection
- 322 Card Detection
- 323 SCI Data Transfer Mode
- 325 Interrupt Generator
- 326 PDMA Interface
- 326 Register Map
- 327 Register Descriptions
- 327 SCI Control Register – CR
- 329 SCI Status Register – SR
- 330 SCI Contact Control Register – CCR
- 331 SCI Elementary Time Unit Register – ETUR
- 332 SCI Guard Time Register – GTR
- 333 SCI Waiting Time Register – WTR
- 334 SCI Interrupt Enable Register – IER
- 335 SCI Interrupt Pending Register – IPR
- 338 SCI Prescaler Register – PSCR
- 339 Introduction
- 339 Features
- 340 Functional Description
- 340 S Master and Slave Mode
- 341 S Clock Rate Generator
- 343 S Interface Format
- 350 FIFO Control and Arrangement
- 351 PDMA and Interrupt
- 351 Register Map
- 352 Register Descriptions
- 352 S Control Register – I2SCR
- 354 S Interrupt Enable Register – I2SIER
- 355 S Clock Divider Register – I2SCDR
- 356 S TX Data Register – I2STXDR
- 356 S RX Data Register – I2SRXDR
- 357 S FIFO Control Register – I2SFCR
- 354 December
- 358 S Status Register – I2SSR
- 360 S Rate Counter Value Register – I2SRCNTR
- 361 19 Analog to Digital Converter (ADC)
- 361 Introduction
- 362 Features
- 363 Functional Descriptions
- 363 ADC Clock Setup
- 363 Channel Selection
- 363 Conversion Mode
- 366 Start Conversion on External Event
- 367 Sampling Time Setting
- 367 Data Format
- 367 Analog Watchdog
- 368 Interrupts
- 368 PDMA Request
- 368 Voltage Reference Generator
- 369 Voltage Monitor
- 369 Register Map
- 370 Register Descriptions
- 370 ADC Conversion Control Register – ADCCR
- 372 ADC Conversion List Register 0 – ADCLST
- 373 ADC Conversion List Register 1 – ADCLST
- 374 ADC Input Sampling Time Register – ADCSTR
- 375 ADC Conversion Data Register y – ADCDRy, y
- 376 ADC Trigger Control Register – ADCTCR
- 377 ADC Trigger Source Register – ADCTSR
- 378 ADC Watchdog Control Register – ADCWCR
- 380 ADC Watchdog Threshold Register – ADCTR
- 381 ADC Interrupt Enable Register – ADCIER
- 382 ADC Interrupt Raw Status Register – ADCIRAW
- 383 ADC Interrupt Status Register – ADCISR
- 384 ADC Interrupt Clear Register – ADCICLR
- 385 ADC DMA Request Register – ADCDMAR
- 386 Voltage Reference Control Register – VREFCR
- 387 Voltage Reference Value Register – VREFVALR
- 388 20 Comparator (CMP)
- 388 Introduction
- 388 Features
- 389 Functional Descriptions
- 389 Comparator Inputs and Output
- 389 Comparator Voltage Reference
- 390 Interrupts and Wakeup
- 388 December
- 391 Power Mode and Hysteresis
- 391 Comparator Write-Protected Mechanism
- 391 Register Map
- 392 Register Descriptions
- 392 Comparator Control Register n – CMPCRn, n = 0 or
- 394 Comparator Voltage Reference Value Register n – CVRVALRn, n = 0 or
- 395 Comparator Interrupt Enable Register n – CMPIERn, n = 0 or
- 396 Comparator Transition Flag Register n – CMPTFRn, n = 0 or
- 397 21 Digital to Analog Converter (DAC)
- 397 Introduction
- 397 Features
- 398 Function Descriptions
- 398 DAC Channel Enable
- 398 DAC Operation Mode
- 398 DAC Asynchronous Conversion
- 399 DAC Synchronous Conversion
- 400 DAC Output Voltage
- 400 Register Map
- 401 Register Descriptions
- 402 DAC Channel 0 Control Register – DAC0CR
- 403 DAC Channel 0 Data Holding Register – DAC0DHR
- 404 DAC Channel 0 Data Output Register – DAC0DOR
- 405 DAC Channel 1 Control Register – DAC1CR
- 406 DAC Channel 1 Data Holding Register – DAC1DHR
- 407 DAC Channel 1 Data Output Register – DAC1DOR
- 408 22 General-Purpose Timer (GPTM)
- 408 Introduction
- 409 Features
- 409 Functional Descriptions
- 409 Counter Mode
- 411 Clock Controller
- 413 Trigger Controller
- 414 Slave Controller
- 416 Master Controller
- 417 Channel Controller
- 419 Input Stage
- 421 Quadrature Decoder
- 422 Output Stage
- 426 Update Management
- 427 Single Pulse Mode
- 419 December
- 429 Asymmetric PWM Mode
- 429 Timer Interconnection
- 431 Trigger Peripherals Start
- 432 PDMA Request
- 433 Register Map
- 434 Register Descriptions
- 439 Timer Control Register – CTR
- 454 Channel Control Register – CHCTR
- 456 Timer PDMA/Interrupt Control Register – DICTR
- 458 Timer Event Generator Register – EVGR
- 459 Timer Interrupt Status Register – INTSR
- 462 Timer Counter Register – CNTR
- 463 Timer Prescaler Register – PSCR
- 464 Timer Counter-Reload Register – CRR
- 465 Channel 0 Capture/Compare Register – CH0CCR
- 466 Channel 1 Capture/Compare Register – CH1CCR
- 467 Channel 2 Capture/Compare Register – CH2CCR
- 468 Channel 3 Capture/Compare Register – CH3CCR
- 469 Channel 0 Asymmetric Compare Register – CH0ACR
- 469 Channel 1 Asymmetric Compare Register – CH1ACR
- 470 Channel 2 Asymmetric Compare Register – CH2ACR
- 470 Channel 3 Asymmetric Compare Register – CH3ACR
- 471 23 Pulse-Width-Modulation Timer (PWM)
- 471 Introduction
- 472 Features
- 472 Functional Descriptions
- 472 Counter Mode
- 475 Clock Controller
- 476 Trigger Controller
- 477 Slave Controller
- 479 Master Controller
- 480 Channel Controller
- 475 December
- 480 Output Stage
- 484 Update Management
- 484 Single Pulse Mode
- 487 Asymmetric PWM Mode
- 487 Timer Interconnection
- 490 Trigger Peripherals Start
- 490 PDMA Request
- 491 Register Map
- 492 Register Descriptions
- 497 Timer Control Register – CTR
- 506 Channel Control Register – CHCTR
- 508 Timer PDMA/Interrupt Control Register – DICTR
- 509 Timer Event Generator Register – EVGR
- 510 Timer Interrupt Status Register – INTSR
- 512 Timer Counter Register – CNTR
- 512 Timer Prescaler Register – PSCR
- 513 Timer Counter-Reload Register – CRR
- 513 Channel 0 Compare Register – CH0CR
- 514 Channel 1 Compare Register – CH1CR
- 514 Channel 2 Compare Register – CH2CR
- 515 Channel 3 Compare Register – CH3CR
- 515 Channel 0 Asymmetric Compare Register – CH0ACR
- 516 Channel 1 Asymmetric Compare Register – CH1ACR
- 516 Channel 2 Asymmetric Compare Register – CH2ACR
- 517 Channel 3 Asymmetric Compare Register – CH3ACR
- 518 24 Single-Channel Timer (SCTM)
- 518 Introduction
- 519 Features
- 519 Functional Descriptions
- 519 Counter Mode
- 520 Clock Controller
- 521 Trigger Controller
- 522 Slave Controller
- 524 Channel Controller
- 526 Input Stage
- 520 December
- 527 Output Stage
- 529 Update Management
- 530 Register Map
- 531 Register Descriptions
- 534 Timer Control Register – CTR
- 538 Channel Control Register – CHCTR
- 540 Timer Interrupt Control Register – DICTR
- 541 Timer Event Generator Register – EVGR
- 542 Timer Interrupt Status Register – INTSR
- 543 Timer Counter Register – CNTR
- 544 Timer Prescaler Register – PSCR
- 545 Timer Counter Reload Register – CRR
- 546 Channel Capture/Compare Register – CHCCR
- 547 25 Basic Function Timer (BFTM)
- 547 Introduction
- 547 Features
- 548 Functional Description
- 548 Repetitive Mode
- 549 One Shot Mode
- 549 Trigger ADC Start
- 550 Register Map
- 550 Register Descriptions
- 550 BFTM Control Register – BFTMCR
- 551 BFTM Status Register – BFTMSR
- 552 BFTM Counter Value Register – BFTMCNTR
- 552 BFTM Compare Value Register – BFTMCMPR
- 553 26 Watchdog Timer (WDT)
- 553 Introduction
- 554 Features
- 554 Functional Description
- 556 Register Map
- 556 Register Descriptions
- 556 Watchdog Timer Control Register – WDTCR
- 557 Watchdog Timer Mode Register 0 – WDTMR
- 558 Watchdog Timer Mode Register 1 – WDTMR
- 559 Watchdog Timer Status Register – WDTSR
- 556 December
- 560 Watchdog Timer Protection Register – WDTPR
- 561 Watchdog Timer Clock Selection Register – WDTCSR
- 562 27 Real Time Clock (RTC)
- 562 Introduction
- 562 Features
- 563 Functional Descriptions
- 563 RTC Related Register Reset
- 563 Reading RTC Register
- 564 RTC Counter Operation
- 564 Interrupt and Wakeup Control
- 566 Register Map
- 566 Register Descriptions
- 566 RTC Counter Register – RTCCNT
- 567 RTC Compare Register – RTCCMP
- 568 RTC Control Register – RTCCR
- 570 RTC Status Register – RTCSR
- 571 RTC Interrupt and Wakeup Enable Register – RTCIWEN
- 572 28 Cyclic Redundancy Check (CRC)
- 572 Introduction
- 572 Features
- 573 Functional Descriptions
- 573 CRC Computation
- 573 Byte and Bit Reversal for CRC Computation
- 574 CRC with PDMA
- 574 Register Map
- 574 Register Descriptions
- 574 CRC Control Register – CRCCR
- 575 CRC Seed Register – CRCSDR
- 576 CRC Checksum Register – CRCCSR
- 577 CRC Data Register – CRCDR
- 578 29 Peripheral Direct Memory Access (PDMA)
- 578 Introduction
- 578 Features
- 579 Functional Description
- 579 AHB Master
- 579 PDMA Channel
- 579 PDMA Request Mapping
- 580 Channel Transfer
- 580 Channel Priority
- 579 December
- 581 Transfer Request
- 581 Address Mode
- 582 Auto-Reload
- 582 Transfer Interrupt
- 582 Register Map
- 584 Register Descriptions
- 584 PDMA Channel n Control Register – PDMACHnCR, n
- 586 PDMA Channel n Source Address Register – PDMACHnSADR, n
- 587 PDMA Channel n Destination Address Register – PDMACHnDADR, n
- 588 PDMA Channel n Transfer Size Register – PDMACHnTSR, n
- 589 PDMA Channel n Current Transfer Size Register – PDMACHnCTSR, n
- 590 PDMA Interrupt Status Register – PDMAISR
- 591 PDMA Interrupt Status Clear Register – PDMAISCR
- 592 PDMA Interrupt Enable Register – PDMAIER
- 594 30 Divider (DIV)
- 594 Introduction
- 594 Features
- 594 Functional Descriptions
- 595 Register Map
- 595 Register Descriptions
- 595 Divider Control Register – CR
- 596 Dividend Data Register – DDR
- 596 Divisor Data Register – DSR
- 597 Quotient Data Register – QTR
- 597 Remainder Data Register – RMR
- 598 31 Liquid Crystal Display Controller (LCD)
- 598 Introduction
- 599 Features
- 599 Functional Descriptions
- 599 Frequency Generator
- 601 Common and Segment Driver
- 610 LCD Drive Selection
- 611 High Drive Duration
- 611 Dead Time
- 613 LCD Low-power Modes
- 613 LCD Interrupts
- 614 Flowchart
- 615 Register Map
- 616 Register Descriptions
- 616 LCD Control Register – LCDCR
- 613 December
- 618 LCD Frame Control Register – LCDFCR
- 620 LCD Interrupt Enable Register – LCDIER
- 621 LCD Status Register – LCDSR
- 622 LCD Status Clear Register – LCDSCR
- 623 LCD RAM – LCDRAM
- 624 32 AES Encrypt/Decrypt Interface (AES)
- 624 Introduction
- 624 Features
- 625 Functional Descriptions
- 625 AES Mode Description
- 627 AES Status
- 627 AES PDMA Interface
- 628 AES Interrupt
- 628 AES Initial Vector
- 629 AES Word Swap
- 629 Register Map
- 630 Register Descriptions
- 630 AES Control Register – AESCR
- 631 AES Status Register – AESSR
- 632 AES DMA Register – AESDMAR
- 633 AES Interrupt Status Register – AESISR
- 634 AES Interrupt Enable Register – AESIER
- 635 AES DATA Input Register – AESDINR
- 635 AES DATA Output Register – AESDOUTR
- 636 AES Key Register n – AESKEYRn, n
- 636 AES Initial Vector Register n – AESIVRn, n
- 634 December