32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

26

Watchdog Timer (WDT)

Introduction

The Watchdog Timer is a hardware timing circuitry that can be used to detect a system lock-up due to software trapped in a deadlock. The Watchdog Timer can be operated in a reset mode. The

Watchdog Timer will generate a reset when the counter counts down to a zero value. Therefore, the software should reload the counter value before a Watchdog Timer underflow occurs. In addition, a reset is also generated if the software reloads the counter before it reaches a delta value. That means that the Watchdog Timer prevents a software deadlock that continuously triggers the Watchdog, the reload must occur when the Watchdog Timer value has a value within a limited window of 0 and WDTD. The Watchdog Timer counter can be stopped when the processor is in the debug or the three sleep modes. The register write protection function can be enabled to prevent an unexpected change in the Watchdog Timer configuration.

WDTV

WDTRS

RSKEY[15:0]

LSI RC

32 kHz

LSE OSC

32.768 kHz

0

1

WDTEN

WDTSRC

CK_WDT

Clear

Prescaler

1, /2, /4, /8,

… /128

WPSC[2:0]

Reload

12-bit

Down-Counter

WDTD

Underflow

WDTUF

WDTERR

WDT Error

WDT_RSTn

WDTRSTEN

Read WDTSR Register

Figure 195. Watchdog Timer Block Diagram

Rev. 1.00 553 of 637 December 28, 2020