Interrupts and Status. Holtek HT32F5828

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Interrupts and Status

The USART can generate interrupts when the following events occur and the corresponding interrupt enable bits are set:

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Receive FIFO time-out interrupt: An interrupt is generated when the USART receive FIFO is not empty and does not receive a new data package during the specified time-out interval.

Receiver line status interrupts: The interrupts are generated when the USART receiver overrun error, parity error, framing error and break events occur.

Transmit FIFO threshold level interrupt: An interrupt is generated when the data to be transmitted in the USART Transmit FIFO is less than the specified threshold level.

Transmit complete interrupt: An interrupt is generated when the Transmit FIFO is empty and the content of the transmit shift register (TSR) is also completely shifted.

Receive FIFO threshold level interrupt: An interrupt is generated when the FIFO received data amount has reached the specified threshold level.

PDMA Interface

The PDMA interface is integrated in the USART. The PDMA function can be enabled by setting the TXDMAEN or RXDMAEN bit in the USRCR register to 1 in the transmit or receive mode respectively. When the data to be transmitted in the USART Transmit FIFO is less than the TX

FIFO threshold level specified by the TXTL field in the USRFCR register and the TXDMAEN bit is set to 1, the PDMA function will be activated to move data from a source location into the

USART TX FIFO.

Similarly, when the received data amount in the receive FIFO is equal to the RX FIFO threshold level specified by the RXTL field in the USRFCR register and the RXDMAEN bit is set to 1, the

PDMA function will be activated to move data from the USART RX FIFO to a specific destination location. For a more detailed description about the PDMA configurations, refer to the PDMA chapter.

Register Map

The following table shows the USART registers and reset values.

Table 43. USART Register Map

Register Offset

USRDR 0x000

USRCR 0x004

Description

USART Data Register

USART Control Register

USRFCR

USRIER

USRSIFR

USRTPR

IrDACR

RS485CR

0x008

0x00C

0x010

0x014

0x018

0x01C

SYNCR

USRDLR

0x020

0x024

USRTSTR 0x028

USART FIFO Control Register

USART Interrupt Enable Register

USART Status & Interrupt Flag Register

USART Timing Parameter Register

USART IrDA Control Register

USART RS485 Control Register

USART Synchronous Control Register

USART Divider Latch Register

USART Test Register

Reset Value

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0980

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0000

0x0000_0010

0x0000_0000

Rev. 1.00 291 of 637 December 28, 2020