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32-Bit Arm ®
HT32F5828
Cortex ® -M0+ MCU
Timer Control Register – CTR
This register specifies the timer enable bit (TME), CRR buffer enable bit (CRBE) and Channel PDMA selection bit (CHCCDS).
Offset: 0x010
Reset value: 0x0000_0000
31 30 29 26 25 24
Type/Reset
Type/Reset
Type/Reset
Type/Reset
23
15
7
22
14
6
21
13
5
28
20
Reserved
27
Reserved
19
12
4
Reserved
11
Reserved
3
18
10
2
17
9
16
CHCCDS
RW 0
8
1
CRBE
0
TME
RW 0 RW 0
Bits
[16]
[1]
[0]
Field
CHCCDS
CRBE
TME
Descriptions
Channel PDMA event selection
0: Channel PDMA request derived from the channel capture/compare event.
1: Channel PDMA request derived from the Update event.
Counter-Reload register Buffer Enable
0: Counter-reload register can be updated immediately
1: Counter-reload register can not be updated until the update event occurs
Timer Enable bit
0: GPTM off
1: GPTM on – GPTM functions normally
When the TME bit is cleared to 0, the counter is stopped and the GPTM consumes no power in any operation mode except for the single pulse mode and the slave trigger mode. In these two modes the TME bit can automatically be set to 1 by hardware which permits all the GPTM registers to function normally.
Rev. 1.00 439 of 637 December 28, 2020
32-Bit Arm ®
HT32F5828
Cortex ® -M0+ MCU
Channel 0 Input Configuration Register – CH0ICFR
This register specifies the channel 0 input mode configuration.
Offset: 0x020
Reset value: 0x0000_0000
30 29 28 31
TI0SRC
Type/Reset RW 0
23
Type/Reset
15
Type/Reset
7
Type/Reset
22
14
6
21
Reserved
13
5
Reserved
20
12
4
27
Reserved
26 25 24
19 18
CH0PSC
17 16
CH0CCS
RW 0 RW 0 RW 0 RW 0
11
Reserved
10 9 8
3 2 1
TI0F
0
RW 0 RW 0 RW 0 RW 0
Bits
[31]
[19:18]
[17:16]
Field
TI0SRC
CH0PSC
CH0CCS
Descriptions
Channel 0 Input Source TI0 Selection
0: The GT_CH0 pin is connected to channel 0 input TI0
1: The XOR operation output of the GT_CH0, GT_CH1, and GT_CH2 pins are connected to the channel 0 input TI0
Channel 0 Capture Input Source Prescaler Setting
These bits define the effective events of the channel 0 capture input. Note that the prescaler is reset once the Channel 0 Capture/Compare Enable bit, CH0E, in the
Channel Control register named CHCTR is cleared to 0.
00: No prescaler, channel 0 capture input signal is chosen for each active event
01: Channel 0 Capture input signal is chosen for every 2 events
10: Channel 0 Capture input signal is chosen for every 4 events
11: Channel 0 Capture input signal is chosen for every 8 events
Channel 0 Capture/Compare Selection
00: Channel 0 is configured as an output
01: Channel 0 is configured as an input derived from the TI0 signal
10: Channel 0 is configured as an input derived from the TI1 signal
11: Channel 0 is configured as an input which comes from the TRCED signal derived from the Trigger Controller
Note: The CH0CCS field can be accessed only when the CH0E bit is cleared to 0.
Rev. 1.00 440 of 637 December 28, 2020
32-Bit Arm ®
HT32F5828
Cortex ® -M0+ MCU
Bits
[3:0]
Field
TI0F
Descriptions
Channel 0 Input Source TI0 Filter Setting
These bits define the frequency divided ratio used to sample the TI0 signal. The
Digital filter in the GPTM is an N-event counter where N is defined as how many valid transitions are necessary to output a filtered signal.
0000: No filter, the sampling clock is f
SYSTEM
0001: f sampling
0010: f
0011: f
0100: f sampling sampling sampling
0101: f sampling
0110: f sampling
0111: f sampling
1000: f sampling
= f
= f
= f
= f
DTS
= f
= f
= f
CLKIN
CLKIN
CLKIN
DTS
DTS
DTS
= f
DTS
, N = 2
, N = 4
, N = 8
/ 2, N = 6
/ 2, N = 8
/ 4, N = 6
/ 4, N = 8
/ 8, N = 6
1001: f
1010: f
1011: f
1100: f sampling sampling sampling sampling
1101: f sampling
1110: f sampling
1111: f sampling
= f
= f
= f
= f
= f
DTS
= f
DTS
= f
DTS
DTS
DTS
DTS
DTS
/ 8, N = 8
/ 16, N = 5
/ 16, N = 6
/ 16, N = 8
/ 32, N = 5
/ 32, N = 6
/ 32, N = 8
Channel 1 Input Configuration Register – CH1ICFR
This register specifies the channel 1 input mode configuration.
Offset: 0x024
Reset value: 0x0000_0000
31 30 29 28
Type/Reset
Type/Reset
Type/Reset
Type/Reset
23
15
7
22
14
6
21
Reserved
13
5
Reserved
20
12
4
27
Reserved
26 25 24
19 18
CH1PSC
17 16
CH1CCS
RW 0 RW 0 RW 0 RW 0
11
Reserved
10 9 8
3 2 1
TI1F
0
RW 0 RW 0 RW 0 RW 0
Bits
[19:18]
Field
CH1PSC
Descriptions
Channel 1 Capture Input Source Prescaler Setting
These bits define the effective events of the channel 1 capture input. Note that the prescaler is reset once the Channel 1 Capture/Compare Enable bit, CH1E, in the
Channel Control register named CHCTR is cleared to 0.
00: No prescaler, channel 1 capture input signal is chosen for each active event
01: Channel 1 Capture input signal is chosen for every 2 events
10: Channel 1 Capture input signal is chosen for every 4 events
11: Channel 1 Capture input signal is chosen for every 8 events
Rev. 1.00 441 of 637 December 28, 2020
32-Bit Arm ®
HT32F5828
Cortex ® -M0+ MCU
Bits
[17:16]
[3:0]
Field
CH1CCS
TI1F
Descriptions
Channel 1 Capture/Compare Selection
00: Channel 1 is configured as an output
01: Channel 1 is configured as an input derived from the TI1 signal
10: Channel 1 is configured as an input derived from the TI0 signal
11: Channel 1 is configured as an input which comes from the TRCED signal derived from the Trigger Controller
Note: The CH1CCS field can be accessed only when the CH1E bit is cleared to 0.
Channel 1 Input Source TI1 Filter Setting
These bits define the frequency divided ratio used to sample the TI1 signal. The
Digital filter in the GPTM is an N-event counter where N is defined as how many valid transitions are necessary to output a filtered signal.
0000: No filter, the sampling clock is f
SYSTEM
0001: f sampling
0010: f
0011: f
0100: f sampling sampling sampling
0101: f sampling
0110: f sampling
0111: f sampling
1000: f sampling
= f
= f
= f
= f
DTS
= f
= f
= f
CLKIN
CLKIN
CLKIN
DTS
DTS
DTS
= f
DTS
, N = 2
, N = 4
, N = 8
/ 2, N = 6
/ 2, N = 8
/ 4, N = 6
/ 4, N = 8
/ 8, N = 6
1001: f
1010: f
1011: f
1100: f sampling sampling sampling sampling
1101: f sampling
1110: f sampling
1111: f sampling
= f
= f
= f
= f
= f
DTS
= f
DTS
= f
DTS
DTS
DTS
DTS
DTS
/ 8, N = 8
/ 16, N = 5
/ 16, N = 6
/ 16, N = 8
/ 32, N = 5
/ 32, N = 6
/ 32, N = 8
Rev. 1.00 442 of 637 December 28, 2020
32-Bit Arm ®
HT32F5828
Cortex ® -M0+ MCU
Channel 2 Input Configuration Register – CH2ICFR
This register specifies the channel 2 input mode configuration.
Offset: 0x028
Reset value: 0x0000_0000
31 30 29 28
Type/Reset
Type/Reset
Type/Reset
Type/Reset
23
15
7
22
14
6
21
Reserved
13
5
Reserved
20
12
4
27
Reserved
26 25 24
19 18
CH2PSC
17 16
CH2CCS
RW 0 RW 0 RW 0 RW 0
11
Reserved
10 9 8
3 2 1
TI2F
0
RW 0 RW 0 RW 0 RW 0
Bits
[19:18]
[17:16]
Field
CH2PSC
CH2CCS
Descriptions
Channel 2 Capture Input Source Prescaler Setting
These bits define the effective events of the channel 2 capture input. Note that the prescaler is reset once the Channel 2 Capture/Compare Enable bit, CH2E, in the
Channel Control register named CHCTR is cleared to 0.
00: No prescaler, channel 2 capture input signal is chosen for each active event
01: Channel 2 Capture input signal is chosen for every 2 events
10: Channel 2 Capture input signal is chosen for every 4 events
11: Channel 2 Capture input signal is chosen for every 8 events
Channel 2 Capture/Compare Selection
00: Channel 2 is configured as an output
01: Channel 2 is configured as an input derived from the TI2 signal
10: Channel 2 is configured as an input derived from the TI3 signal
11: Channel 2 is configured as an input which comes from the TRCED signal derived from the Trigger Controller
Note: The CH2CCS field can be accessed only when the CH2E bit is cleared to 0.
Rev. 1.00 443 of 637 December 28, 2020
32-Bit Arm ®
HT32F5828
Cortex ® -M0+ MCU
Bits
[3:0]
Field
TI2F
Descriptions
Channel 2 Input Source TI2 Filter Setting
These bits define the frequency divided ratio used to sample the TI2 signal. The
Digital filter in the GPTM is an N-event counter where N is defined as how many valid transitions are necessary to output a filtered signal.
0000: No filter, the sampling clock is f
SYSTEM
0001: f sampling
0010: f
0011: f
0100: f sampling sampling sampling
0101: f sampling
0110: f sampling
0111: f sampling
1000: f sampling
= f
= f
= f
= f
DTS
= f
= f
= f
CLKIN
CLKIN
CLKIN
DTS
DTS
DTS
= f
DTS
, N = 2
, N = 4
, N = 8
/ 2, N = 6
/ 2, N = 8
/ 4, N = 6
/ 4, N = 8
/ 8, N = 6
1001: f
1010: f
1011: f
1100: f sampling sampling sampling sampling
1101: f sampling
1110: f sampling
1111: f sampling
= f
= f
= f
= f
= f
DTS
= f
DTS
= f
DTS
DTS
DTS
DTS
DTS
/ 8, N = 8
/ 16, N = 5
/ 16, N = 6
/ 16, N = 8
/ 32, N = 5
/ 32, N = 6
/ 32, N = 8
Channel 3 Input Configuration Register – CH3ICFR
This register specifies the channel 3 input mode configuration.
Offset: 0x02C
Reset value: 0x0000_0000
31 30 29 28
Type/Reset
Type/Reset
Type/Reset
Type/Reset
23
15
7
22
14
6
21
Reserved
13
5
Reserved
20
12
4
27
Reserved
26 25 24
19 18
CH3PSC
17 16
CH3CCS
RW 0 RW 0 RW 0 RW 0
11
Reserved
10 9 8
3 2 1
TI3F
0
RW 0 RW 0 RW 0 RW 0
Bits
[19:18]
Field
CH3PSC
Descriptions
Channel 3 Capture Input Source Prescaler Setting
These bits define the effective events of the channel 3 capture input. Note that the prescaler is reset once the Channel 3 Capture/Compare Enable bit, CH3E, in the
Channel Control register named CHCTR is cleared to 0.
00: No prescaler, channel 3 capture input signal is chosen for each active event
01: Channel 3 Capture input signal is chosen for every 2 events
10: Channel 3 Capture input signal is chosen for every 4 events
11: Channel 3 Capture input signal is chosen for every 8 events
Rev. 1.00 444 of 637 December 28, 2020
32-Bit Arm ®
HT32F5828
Cortex ® -M0+ MCU
Bits
[17:16]
[3:0]
Field
CH3CCS
TI3F
Descriptions
Channel 3 Capture/Compare Selection
00: Channel 3 is configured as an output
01: Channel 3 is configured as an input derived from the TI3 signal
10: Channel 3 is configured as an input derived from the TI2 signal
11: Channel 3 is configured as an input which comes from the TRCED signal derived from the Trigger Controller
Note: The CH3CCS field can be accessed only when the CH3E bit is cleared to 0.
Channel 3 Input Source TI3 Filter Setting
These bits define the frequency divided ratio used to sample the TI3 signal. The
Digital filter in the GPTM is an N-event counter where N is defined as how many valid transitions are necessary to output a filtered signal.
0000: No filter, the sampling clock is f
SYSTEM
0001: f sampling
0010: f
0011: f
0100: f sampling sampling sampling
0101: f sampling
0110: f sampling
0111: f sampling
1000: f sampling
= f
= f
= f
= f
DTS
= f
= f
= f
CLKIN
CLKIN
CLKIN
DTS
DTS
DTS
= f
DTS
, N = 2
, N = 4
, N = 8
/ 2, N = 6
/ 2, N = 8
/ 4, N = 6
/ 4, N = 8
/ 8, N = 6
1001: f
1010: f
1011: f
1100: f sampling sampling sampling sampling
1101: f sampling
1110: f sampling
1111: f sampling
= f
= f
= f
= f
= f
DTS
= f
DTS
= f
DTS
DTS
DTS
DTS
DTS
/ 8, N = 8
/ 16, N = 5
/ 16, N = 6
/ 16, N = 8
/ 32, N = 5
/ 32, N = 6
/ 32, N = 8
Rev. 1.00 445 of 637 December 28, 2020
32-Bit Arm ®
HT32F5828
Cortex ® -M0+ MCU
Channel 0 Output Configuration Register – CH0OCFR
This register specifies the channel 0 output mode configuration.
Offset: 0x040
Reset value: 0x0000_0000
31
Type/Reset
Type/Reset
Type/Reset
Type/Reset
23
15
7
30
22
29
21
28
20
27
Reserved
19
Reserved
26
18
25
17
24
16
14 13 12 11
Reserved
6 5 4 3
Reserved CH0IMAE CH0PRE Reserved
RW 0 RW 0
10
2
9
1
CH0OM[2:0]
8
CH0OM[3]
RW 0
0
RW 0 RW 0 RW 0
Bits
[5]
[4]
Field Descriptions
CH0IMAE Channel 0 Immediate Active Enable
0: No action
1: Single pulse Immediate Active Mode is enabled
The CH0OREF signal will be forced to the compare matched level immediately after an available trigger event occurs irrespective of the result of the comparison between the CNTR and the CH0CCR values.
The effective duration ends automatically at the next overflow or underflow event.
Note: The CH0IMAE bit is available only if the channel 0 is configured to be operated in the PWM mode 1 or PWM mode 2.
CH0PRE Channel 0 Capture/Compare Register (CH0CCR) Preload Enable
0: CH0CCR preload function is disabled
The CH0CCR register can be immediately assigned a new value when the CH0PRE bit is cleared to 0 and the updated CH0CCR value is used immediately.
1: CH0CCR preload function is enabled
The new CH0CCR value will not be transferred to its shadow register until the update event occurs.
Rev. 1.00 446 of 637 December 28, 2020
32-Bit Arm ®
HT32F5828
Cortex ® -M0+ MCU
Bits
[8][2:0]
Field Descriptions
CH0OM[3:0] Channel 0 Output Mode Setting
These bits define the functional types of the output reference signal CH0OREF.
0000: No Change
0001: Output 0 on compare match
0010: Output 1 on compare match
0011: Output toggles on compare match
0100: Force inactive – CH0OREF is forced to 0
0101: Force active – CH0OREF is forced to 1
0110: PWM mode 1
- During up-counting, channel 0 has an active level when CNTR <
CH0CCR or otherwise has an inactive level.
- During down-counting, channel 0 has an inactive level when CNTR >
CH0CCR or otherwise has an active level.
0111: PWM mode 2
- During up-counting, channel 0 is has an inactive level when CNTR <
CH0CCR or otherwise has an active level.
- During down-counting, channel 0 has an active level when CNTR >
CH0CCR or otherwise has an inactive level.
1110: Asymmetric PWM mode 1
- During up-counting, channel 0 has an active level when CNTR <
CH0CCR or otherwise has an inactive level.
- During down-counting, channel 0 has an inactive level when CNTR >
CH0ACR or otherwise has an active level.
1111: Asymmetric PWM mode 2
- During up-counting, channel 0 has an inactive level when CNTR <
CH0CCR or otherwise has an active level.
- During down-counting, channel 0 has an active level when CNTR >
CH0ACR or otherwise has an inactive level
Note: When channel 0 is used as asymmetric PWM output mode, the Counter Mode
Selection bit in Counter Configuration Register must be configured as Centeraligned Counting mode (CMSEL = 0x1/0x2/0x3).
Rev. 1.00 447 of 637 December 28, 2020
32-Bit Arm ®
HT32F5828
Cortex ® -M0+ MCU
Channel 1 Output Configuration Register – CH1OCFR
This register specifies the channel 1 output mode configuration.
Offset: 0x044
Reset value: 0x0000_0000
31
Type/Reset
Type/Reset
Type/Reset
Type/Reset
23
15
7
30
22
29
21
28
20
27
Reserved
19
Reserved
26
18
25
17
24
16
14 13 12 11
Reserved
6 5 4 3
Reserved CH1IMAE CH1PRE Reserved
RW 0 RW 0
10
2
9
1
CH1OM[2:0]
8
CH1OM[3]
RW 0
0
RW 0 RW 0 RW 0
Bits
[5]
[4]
Field Descriptions
CH1IMAE Channel 1 Immediate Active Enable
0: No action
1: Single pulse Immediate Active Mode is enabled
The CH1OREF signal will be forced to the compare matched level immediately after an available trigger event occurs irrespective of the result of the comparison between the CNTR and the CH1CCR values.
The effective duration ends automatically at the next overflow or underflow event.
Note: The CH1IMAE bit is available only if the channel 1 is configured to be operated in the PWM mode 1 or PWM mode 2.
CH1PRE Channel 1 Capture/Compare Register (CH1CCR) Preload Enable
0: CH1CCR preload function is disabled.
The CH1CCR register can be immediately assigned a new value when the CH1PRE bit is cleared to 0 and the updated CH1CCR value is used immediately.
1: CH1CCR preload function is enabled
The new CH1CCR value will not be transferred to its shadow register until the update event occurs.
Rev. 1.00 448 of 637 December 28, 2020
32-Bit Arm ®
HT32F5828
Cortex ® -M0+ MCU
Bits
[8][2:0]
Field Descriptions
CH1OM[3:0] Channel 1 Output Mode Setting
These bits define the functional types of the output reference signal CH1OREF.
0000: No Change
0001: Output 0 on compare match
0010: Output 1 on compare match
0011: Output toggles on compare match
0100: Force inactive – CH1OREF is forced to 0
0101: Force active – CH1OREF is forced to 1
0110: PWM mode 1
- During up-counting, channel 1 has an active level when CNTR <
CH1CCR or otherwise has an inactive level.
- During down-counting, channel 1 has an inactive level when CNTR >
CH1CCR or otherwise has an active level.
0111: PWM mode 2
- During up-counting, channel 1 has an inactive level when CNTR <
CH1CCR or otherwise has an active level.
- During down-counting, channel 1 has an active level when CNTR >
CH1CCR or otherwise has an inactive level.
1110: Asymmetric PWM mode 1
- During up-counting, channel 1 has an active level when CNTR <
CH1CCR or otherwise has an inactive level.
- During down-counting, channel 1 has an inactive level when CNTR >
CH1ACR or otherwise has an active level.
1111: Asymmetric PWM mode 2
- During up-counting, channel 1 has an inactive level when CNTR <
CH1CCR or otherwise has an active level.
- During down-counting, channel 1 has an active level when CNTR >
CH1ACR or otherwise has an inactive level
Note: When channel 1 is used as asymmetric PWM output mode, the Counter Mode
Selection bit in Counter Configuration Register must be configured as Centeraligned Counting mode (CMSEL = 0x1/0x2/0x3).
Rev. 1.00 449 of 637 December 28, 2020
32-Bit Arm ®
HT32F5828
Cortex ® -M0+ MCU
Channel 2 Output Configuration Register – CH2OCFR
This register specifies the channel 2 output mode configuration.
Offset: 0x048
Reset value: 0x0000_0000
31
Type/Reset
Type/Reset
Type/Reset
Type/Reset
23
15
7
30
22
29
21
28
20
27
Reserved
19
Reserved
26
18
25
17
24
16
14 13 12 11
Reserved
6 5 4 3
Reserved CH2IMAE CH2PRE Reserved
RW 0 RW 0
10
2
9
1
CH2OM[2:0]
8
CH2OM[3]
RW 0
0
RW 0 RW 0 RW 0
Bits
[5]
[4]
Field Descriptions
CH2IMAE Channel 2 Immediate Active Enable
0: No action
1: Single pulse Immediate Active Mode is enabled
The CH2OREF signal will be forced to the compare matched level immediately after an available trigger event occurs irrespective of the result of the comparison between the CNTR and the CH2CCR values.
The effective duration ends automatically at the next overflow or underflow event.
Note: The CH2IMAE bit is available only if the channel 2 is configured to be operated in the PWM mode 1 or PWM mode 2.
CH2PRE Channel 2 Capture/Compare Register (CH2CCR) Preload Enable
0: CH2CCR preload function is disabled.
The CH2CCR register can be immediately assigned a new value when the CH2PRE bit is cleared to 0 and the updated CH2CCR value is used immediately.
1: CH2CCR preload function is enabled
The new CH2CCR value will not be transferred to its shadow register until the update event occurs.
Rev. 1.00 450 of 637 December 28, 2020
32-Bit Arm ®
HT32F5828
Cortex ® -M0+ MCU
Bits
[8][2:0]
Field Descriptions
CH2OM[3:0] Channel 2 Output Mode Setting
These bits define the functional types of the output reference signal CH2OREF.
0000: No Change
0001: Output 0 on compare match
0010: Output 1 on compare match
0011: Output toggles on compare match
0100: Force inactive – CH2OREF is forced to 0
0101: Force active – CH2OREF is forced to 1
0110: PWM mode 1
- During up-counting, channel 2 has an active level when CNTR <
CH2CCR or otherwise has an inactive level.
- During down-counting, channel 2 has an inactive level when CNTR >
CH2CCR or otherwise has an active level.
0111: PWM mode 2
- During up-counting, channel 2 has an inactive level when CNTR <
CH2CCR or otherwise has an active level.
- During down-counting, channel 2 has an active level when CNTR >
CH2CCR or otherwise has an inactive level.
1110: Asymmetric PWM mode 1
- During up-counting, channel 2 has an active level when CNTR <
CH2CCR or otherwise has an inactive level.
- During down-counting, channel 2 has an inactive level when CNTR >
CH2ACR or otherwise has an active level.
1111: Asymmetric PWM mode 2
- During up-counting, channel 2 has an inactive level when CNTR <
CH2CCR or otherwise has an active level.
- During down-counting, channel 2 has an active level when CNTR >
CH2ACR or otherwise has an inactive level
Note: When channel 2 is used as asymmetric PWM output mode, the Counter Mode
Selection bit in Counter Configuration Register must be configured as Centeraligned Counting mode (CMSEL = 0x1/0x2/0x3).
Rev. 1.00 451 of 637 December 28, 2020
32-Bit Arm ®
HT32F5828
Cortex ® -M0+ MCU
Channel 3 Output Configuration Register – CH3OCFR
This register specifies the channel 3 output mode configuration.
Offset: 0x04C
Reset value: 0x0000_0000
31
Type/Reset
Type/Reset
Type/Reset
Type/Reset
23
15
7
30
22
29
21
28
20
27
Reserved
19
Reserved
26
18
25
17
24
16
14 13 12 11
Reserved
6 5 4 3
Reserved CH3IMAE CH3PRE Reserved
RW 0 RW 0
10
2
9
1
CH3OM[2:0]
8
CH3OM[3]
RW 0
0
RW 0 RW 0 RW 0
Bits
[5]
[4]
Field Descriptions
CH3IMAE Channel 3 Immediate Active Enable
0: No action
1: Single pulse Immediate Active Mode is enabled
The CH3OREF signal will be forced to the compare matched level immediately after an available trigger event occurs irrespective of the result of the comparison between the CNTR and the CH3CCR values.
The effective duration ends automatically at the next overflow or underflow event.
Note: The CH3IMAE bit is available only if the channel 3 is configured to be operated in the PWM mode 1 or PWM mode 2.
CH3PRE Channel 3 Capture/Compare Register (CH3CCR) Preload Enable
0: CH3CCR preload function is disabled.
The CH3CCR register can be immediately assigned a new value when the CH3PRE bit is cleared to 0 and the updated CH3CCR value is used immediately.
1: CH3CCR preload function is enabled
The new CH3CCR value will not be transferred to its shadow register until the update event occurs.
Rev. 1.00 452 of 637 December 28, 2020
32-Bit Arm ®
HT32F5828
Cortex ® -M0+ MCU
Bits
[8][2:0]
Field Descriptions
CH3OM[3:0] Channel 3 Output Mode Setting
These bits define the functional types of the output reference signal CH3OREF
0000: No Change
0001: Output 0 on compare match
0010: Output 1 on compare match
0011: Output toggles on compare match
0100: Force inactive – CH3OREF is forced to 0
0101: Force active – CH3OREF is forced to 1
0110: PWM mode 1
- During up-counting, channel 3 has an active level when CNTR <
CH3CCR or otherwise has an inactive level.
- During down-counting, channel 3 has an inactive level when CNTR >
CH3CCR or otherwise has an active level.
0111: PWM mode 2
- During up-counting, channel 3 has an inactive level when CNTR <
CH3CCR or otherwise has an active level.
- During down-counting, channel 3 has an active level when CNTR >
CH3CCR or otherwise has an inactive level
1110: Asymmetric PWM mode 1
- During up-counting, channel 3 has an active level when CNTR <
CH3CCR or otherwise has an inactive level.
- During down-counting, channel 3 has an inactive level when CNTR >
CH3ACR or otherwise has an active level.
1111: Asymmetric PWM mode 2
- During up-counting, channel 3 has an inactive level when CNTR <
CH3CCR or otherwise has an active level.
- During down-counting, channel 3 has an active level when CNTR >
CH3ACR or otherwise has an inactive level
Note: When channel 3 is used as asymmetric PWM output mode, the Counter Mode
Selection bit in Counter Configuration Register must be configured as Centeraligned Counting mode (CMSEL = 0x1/0x2/0x3).
Rev. 1.00 453 of 637 December 28, 2020
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