UART Divider Latch Register – URDLR. Holtek HT32F5828

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Bits

[2]

[1]

Field

PEI

OEI

Descriptions

Parity Error Indicator

This bit is set to 1 whenever the received character does not have a valid parity bit.

Writing 1 to this bit clears the flag.

Overrun Error Indicator

An overrun error will occur only after the receive data register is full and when the next character has been completely received in the receive shift register. The character in the receive shift register will be overwritten when a new character is received in the receive shift register after an overrun event occurs, but the data in the receive shift register will not be transferred to the receive data register. The OEI bit is used to indicate event as soon as it happens. Writing 1 to this bit clears the flag.

UART Divider Latch Register – URDLR

The register is used to determine the UART clock divided ratio to generate the appropriate baud rate.

Offset: 0x024

Reset value: 0x0000_0010

31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12 11

BRD

10 9 8

Type/Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0

7 6 5 4 3

BRD

2 1 0

Type/Reset RW 0 RW 0 RW 0 RW 1 RW 0 RW 0 RW 0 RW 0

Bits

[15:0]

Field

BRD

Descriptions

Baud Rate Divider

The 16 bits define the UART clock divider ratio.

Baud Rate = CK_UART / BRD

Where the CK_UART clock is the clock connected to the UART module.

BRD = 16 ~ 65535 for the UART mode

Rev. 1.00 315 of 637 December 28, 2020