Features. Holtek HT32F5828

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Features

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16-bit up/down auto-reload counter

16-bit programmable prescaler that allows division of the prescaler clock source by any factor between 1 and 65536 to generate the counter clock frequency

Up to 4 independent channels for:

● Input Capture function

● Compare Match Output

● Generation of PWM waveform – Edge and Center-aligned Mode

● Single Pulse Mode Output

Encoder interface controller with two inputs using quadrature decoder

Synchronization circuit to control the timer with external signals and to interconnect several timers together

Interrupt/PDMA generation with the following events:

● Update event

●

● Input capture event

●

Trigger event

Output compare match event

GPTM Master/Slave mode controller

Functional Descriptions

Counter Mode

Up-Counting

In this mode the counter counts continuously from 0 to the counter-reload value, which is defined in the CRR register, in a count-up direction. Once the counter reaches the counter-reload value, the Timer Module generates an overflow event and the counter restarts to count once again from

0. This action will continue repeatedly. The counting direction bit DIR in the CNTCFR register should be set to 0 for the up-counting mode.

When the update event is generated by setting the UEVG bit in the EVGR register to 1, the counter value will also be initialized to 0.

Rev. 1.00 409 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

CK_PSC

CNT_EN

CK_CNT

CNTR

CRR

CRR Shadow

Register

PSCR

PSCR Shadow

Register

PSC_CNT

Counter Overflow

Update Event Flag

F5

F2

0

F5

0

0

F3

Write a new value

Figure 114. Up-counting Example

F4 F5

0

0

Update the new value

1

36

0

1

1

1

36

1

0

2

1

Software clearing

0

3

1

Down-Counting

In this mode the counter counts continuously from the counter-reload value, which is defined in the CRR register, to 0 in a count-down direction. Once the counter reaches 0, the Timer module generates an underflow event and the counter restarts to count once again from the counter-reload value. This action will continue repeatedly. The counting direction bit DIR in the CNTCFR register should be set to 1 for the down-counting mode.

When the update event is set by the UEVG bit in the EVGR register, the counter value will also be initialized to the counter-reload value.

CK_PSC

CNT_EN

CK_CNT

CNTR

CRR

CRR Shadow

Register

PSCR

PSCR Shadow

Register

PSC_CNT

Counter Underflow

Update Event Flag

F5

3

0

F5

0

0

2

Write a new value

Figure 115. Down-counting Example

1 0

0

36

Update a new value

1

36

0

35

1

1

36

1

0

34

Software clearing

1

33

0 1

Rev. 1.00 410 of 637 December 28, 2020