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32-Bit Arm ®
HT32F5828
Cortex ® -M0+ MCU
Register Descriptions
PDMA Channel n Control Register – PDMACHnCR, n = 0 ~ 5
This register is used to specify the PDMA channel n data transfer configuration.
Offset: 0x000 (0), 0x018 (1), 0x030 (2), 0x048 (3), 0x060 (4), 0x078 (5)
Reset value: 0x0000_0000
31 30 29 28 27
Reserved
26 25 24
Type/Reset
23 22 21 20 19
Reserved
18 17 16
Type/Reset
15 14 13
Reserved
12 11 10
AUTORLn FIXAENn
9 8
CHnPRI
Type/Reset
7 6 5 4
SRCAMODn SRCAINCn DSTAMODn DSTAINCn
RW 0 RW 0 RW 0 RW 0
3 2 1 0
DWIDTHn SWTRIGn CHnEN
Type/Reset RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0
Bits
[11]
[10]
[9:8]
Field Descriptions
AUTORLn Channel n Auto-Reload Enable Control
0: Disable Auto-Reload function
1: Enable Auto-Reload function
If this bit is set to 1 to enable the auto-reload function, both the channel n current address and the channel n current transfer size will be reloaded with the relevant start value and the PDMA channel n will still be activated when a transfer is complete. If this bit is cleared to 0, the channel n current address and the channel n current transfer size will remain unchanged and the PDMA channel n will be disabled after a transfer completion.
FIXAENn
CHnPRI
Channel n Fixed Address Enable control
0: Disable fixed address function in the circular address mode
1: Enable fixed address function in the circular address mode
Note that this bit is only available when the source or destination address mode is set to be in the circular address mode. For example, the source address mode is set as in the linear address mode and the destination address mode is set as in the circular mode. If this bit is set to enable the fixed address function, then the source address mode will still be in the linear address but the destination address mode will be in the fixed address mode instead of the circular address mode.
Channel n Priority
00: Low
01: Medium
10: High
11: Very high
The CHnPRI field is used to configure the channel priority using the application program. If there are more than one channel which have the same software configured priority level, the channel with the smaller channel number will have priority to transfer one block of data after the arbitration.
Rev. 1.00 584 of 637 December 28, 2020
32-Bit Arm ®
HT32F5828
Cortex ® -M0+ MCU
Bits
[7]
[6]
[5]
[4]
[3:2]
[1]
Field Descriptions
SRCAMODn Channel n Source Address Mode selection
0: Linear address mode
1: Circular address mode
In the linear address mode, the current source address value can be increased or decreased, determined by the SRCAINCn bit value during a complete transfer.
In the circular address mode, the current source address value can be increased or decreased which is also determined by the SRCAINCn bit value during a block transfer and will be loaded with the lower 16-bit value of the PDMACHnSADR register, which will be regarded as the current source address when a block transaction has completed.
SRCAINCn Channel n Source Address Increment control
0: Increment
1: Decrement
This bit is used to determine whether the current source address is increased or decreased during a complete transfer in the linear address mode or a block transfer in the circular address mode.
DSTAMODn Channel n Destination Address Mode selection
0: Linear address mode
1: Circular address mode
In linear address mode, the current destination address value can be increased or decreased, determined by the DSTAINCn bit value during a complete transfer. In the circular address mode, the current destination address value can be increased or decreased which is also determined by the DSTAINCn bit value during a block transfer and will be loaded with the lower 16-bit value of the PDMACHnDADR register, which will be regarded as the current destination address when a block transfer has completed.
DSTAINCn Channel n Destination Address Increment Control
0: Increment
1: Decrement
This bit is used to determine if the current destination address is increased or decreased during a complete transfer in the linear address mode or a block transfer in the circular address mode.
DWIDTHn Data Bit Width selection
00: 8-bit
01: 16-bit
10: 32-bit
11: Reserved
The field is used to select the data bit width of the corresponding PDMA channel n.
SWTRIGn Software Trigger control
0: No operation
1: Software triggered transfer request
Setting this bit will generate a memory-to-memory software transfer request on the corresponding PDMA channel n. It is automatically cleared when a transfer has completely finished.
Rev. 1.00 585 of 637 December 28, 2020
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