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32-Bit Arm ®
HT32F5828
Cortex ® -M0+ MCU
Timer Control Register – CTR
This register specifies the timer enable bit (TME), CRR buffer enable bit (CRBE) and Channel PDMA selection bit (CHCDS).
Offset: 0x010
Reset value: 0x0000_0000
31 30 29 26 25 24
Type/Reset
Type/Reset
Type/Reset
Type/Reset
23
15
7
22
14
6
21
13
5
28
20
Reserved
27
Reserved
19
12
4
Reserved
11
Reserved
3
18
10
2
17
9
16
CHCDS
RW 0
8
1
CRBE
0
TME
RW 0 RW 0
Bits
[16]
[1]
[0]
Field
CHCDS
CRBE
TME
Descriptions
Channel PDMA event selection
0: Channel PDMA request derived from the channel compare event.
1: Channel PDMA request derived from the Update event.
Counter-Reload register Buffer Enable
0: Counter-reload register can be updated immediately
1: Counter-reload register can not be updated until the update event occurs
Timer Enable bit
0: PWM off
1: PWM on
When the TME bit is cleared to 0, the counter is stopped and the PWM consumes no power in any operation mode except for the single pulse mode and the slave trigger mode. In these two modes the TME bit can automatically be set to 1 by hardware which permits all the PWM registers to function normally.
Rev. 1.00 497 of 637 December 28, 2020
32-Bit Arm ®
HT32F5828
Cortex ® -M0+ MCU
Channel 0 Output Configuration Register – CH0OCFR
This register specifies the channel 0 output mode configuration.
Offset: 0x040
Reset value: 0x0000_0000
31
Type/Reset
Type/Reset
Type/Reset
Type/Reset
23
15
7
30
22
29
21
28
20
27
Reserved
19
Reserved
26
18
25
17
24
16
14 13 12 11
Reserved
6 5 4 3
Reserved CH0IMAE CH0PRE Reserved
RW 0 RW 0
10
2
9
1
CH0OM[2:0]
8
CH0OM[3]
RW 0
0
RW 0 RW 0 RW 0
Bits
[5]
[4]
Field Descriptions
CH0IMAE Channel 0 Immediate Active Enable
0: No action
1: Single pulse Immediate Active Mode is enabled
The CH0OREF signal will be forced to the compare matched level immediately after an available trigger event occurs irrespective of the result of the comparison between the CNTR and the CH0CR values.
The effective duration ends automatically at the next overflow or underflow event.
Note: The CH0IMAE bit is available only if the channel 0 is configured to be operated in the PWM mode 1 or PWM mode 2.
CH0PRE Channel 0 Compare Register (CH0CR) Preload Enable
0: CH0CR preload function is disabled
The CH0CR register can be immediately assigned a new value when the
CH0PRE bit is cleared to 0 and the updated CH0CR value is used immediately.
1: CH0CR preload function is enabled
The new CH0CR value will not be transferred to its shadow register until the update event occurs.
Rev. 1.00 498 of 637 December 28, 2020
32-Bit Arm ®
HT32F5828
Cortex ® -M0+ MCU
Bits
[8][2:0]
Field Descriptions
CH0OM[3:0] Channel 0 Output Mode Setting
These bits define the functional types of the output reference signal CH0OREF.
0000: No Change
0001: Output 0 on compare match
0010: Output 1 on compare match
0011: Output toggles on compare match
0100: Force inactive – CH0OREF is forced to 0
0101: Force active – CH0OREF is forced to 1
0110: PWM mode 1
- During up-counting, channel 0 has an active level when CNTR < CH0CR or otherwise has an inactive level.
- During down-counting, channel 0 has an inactive level when CNTR >
CH0CR or otherwise has an active level.
0111: PWM mode 2
- During up-counting, channel 0 is has an inactive level when CNTR <
CH0CR or otherwise has an active level.
- During down-counting, channel 0 has an active level when CNTR >
CH0CR or otherwise has an inactive level.
1110: Asymmetric PWM mode 1
- During up-counting, channel 0 has an active level when CNTR < CH0CR or otherwise has an inactive level.
- During down-counting, channel 0 has an inactive level when CNTR >
CH0ACR or otherwise has an active level.
1111: Asymmetric PWM mode 2
- During up-counting, channel 0 has an inactive level when CNTR <
CH0CR or otherwise has an active level.
- During down-counting, channel 0 has an active level when CNTR >
CH0ACR or otherwise has an inactive level.
Note: When channel 0 is used as asymmetric PWM output mode, the Counter Mode
Selection bit in Counter Configuration Register must be configured as Centeraligned Counting mode (CMSEL = 0x1/0x2/0x3)
Rev. 1.00 499 of 637 December 28, 2020
32-Bit Arm ®
HT32F5828
Cortex ® -M0+ MCU
Channel 1 Output Configuration Register – CH1OCFR
This register specifies the channel 1 output mode configuration.
Offset: 0x044
Reset value: 0x0000_0000
31
Type/Reset
Type/Reset
Type/Reset
Type/Reset
23
15
7
30
22
29
21
28
20
27
Reserved
19
Reserved
26
18
25
17
24
16
14 13 12 11
Reserved
6 5 4 3
Reserved CH1IMAE CH1PRE Reserved
RW 0 RW 0
10
2
9
1
CH1OM[2:0]
8
CH1OM[3]
RW 0
0
RW 0 RW 0 RW 0
Bits
[5]
[4]
Field Descriptions
CH1IMAE Channel 1 Immediate Active Enable
0: No action
1: Single pulse Immediate Active Mode is enabled
The CH1OREF signal will be forced to the compare matched level immediately after an available trigger event occurs irrespective of the result of the comparison between the CNTR and the CH1CR values.
The effective duration ends automatically at the next overflow or underflow event.
Note: The CH1IMAE bit is available only if the channel 1 is configured to be operated in the PWM mode 1 or PWM mode 2.
CH1PRE Channel 1 Compare Register (CH1CR) Preload Enable
0: CH1CR preload function is disabled.
The CH1CR register can be immediately assigned a new value when the CH1PRE bit is cleared to 0 and the updated CH1CR value is used immediately.
1: CH1CR preload function is enabled
The new CH1CR value will not be transferred to its shadow register until the update event occurs.
Rev. 1.00 500 of 637 December 28, 2020
32-Bit Arm ®
HT32F5828
Cortex ® -M0+ MCU
Bits
[8][2:0]
Field Descriptions
CH1OM[3:0] Channel 1 Output Mode Setting
These bits define the functional types of the output reference signal CH1OREF.
0000: No Change
0001: Output 0 on compare match
0010: Output 1 on compare match
0011: Output toggles on compare match
0100: Force inactive – CH1OREF is forced to 0
0101: Force active – CH1OREF is forced to 1
0110: PWM mode 1
- During up-counting, channel 1 has an active level when CNTR < CH1CR or otherwise has an inactive level.
- During down-counting, channel 1 has an inactive level when CNTR >
CH1CR or otherwise has an active level.
0111: PWM mode 2
- During up-counting, channel 1 has an inactive level when CNTR <
CH1CR or otherwise has an active level.
- During down-counting, channel 1 has an active level when CNTR >
CH1CR or otherwise has an inactive level.
1110: Asymmetric PWM mode 1
- During up-counting, channel 1 has an active level when CNTR < CH1CR or otherwise has an inactive level.
- During down-counting, channel 1 has an inactive level when CNTR >
CH1ACR or otherwise has an active level.
1111: Asymmetric PWM mode 2
- During up-counting, channel 1 has an inactive level when CNTR <
CH1CR or otherwise has an active level.
- During down-counting, channel 1 has an active level when CNTR >
CH1ACR or otherwise has an inactive level.
Note: When channel 1 is used as asymmetric PWM output mode, the Counter Mode
Selection bit in Counter Configuration Register must be configured as Centeraligned Counting mode (CMSEL = 0x1/0x2/0x3)
Rev. 1.00 501 of 637 December 28, 2020
32-Bit Arm ®
HT32F5828
Cortex ® -M0+ MCU
Channel 2 Output Configuration Register – CH2OCFR
This register specifies the channel 2 output mode configuration.
Offset: 0x048
Reset value: 0x0000_0000
31
Type/Reset
Type/Reset
Type/Reset
Type/Reset
23
15
7
30
22
29
21
28
20
27
Reserved
19
Reserved
26
18
25
17
24
16
14 13 12 11
Reserved
6 5 4 3
Reserved CH2IMAE CH2PRE Reserved
RW 0 RW 0
10
2
9
1
CH2OM[2:0]
8
CH2OM[3]
RW 0
0
RW 0 RW 0 RW 0
Bits
[5]
[4]
Field Descriptions
CH2IMAE Channel 2 Immediate Active Enable
0: No action
1: Single pulse Immediate Active Mode is enabled
The CH2OREF signal will be forced to the compare matched level immediately after an available trigger event occurs irrespective of the result of the comparison between the CNTR and the CH2CR values.
The effective duration ends automatically at the next overflow or underflow event.
Note: The CH2IMAE bit is available only if the channel 2 is configured to be operated in the PWM mode 1 or PWM mode 2.
CH2PRE Channel 2 Compare Register (CH2CR) Preload Enable
0: CH2CR preload function is disabled.
The CH2CR register can be immediately assigned a new value when the
CH2PRE bit is cleared to 0 and the updated CH2CR value is used immediately.
1: CH2CR preload function is enabled
The new CH2CR value will not be transferred to its shadow register until the update event occurs.
Rev. 1.00 502 of 637 December 28, 2020
32-Bit Arm ®
HT32F5828
Cortex ® -M0+ MCU
Bits
[8][2:0]
Field Descriptions
CH2OM[3:0] Channel 2 Output Mode Setting
These bits define the functional types of the output reference signal CH2OREF.
0000: No Change
0001: Output 0 on compare match
0010: Output 1 on compare match
0011: Output toggles on compare match
0100: Force inactive – CH2OREF is forced to 0
0101: Force active – CH2OREF is forced to 1
0110: PWM mode 1
- During up-counting, channel 2 has an active level when CNTR < CH2CR or otherwise has an inactive level.
- During down-counting, channel 2 has an inactive level when CNTR >
CH2CR or otherwise has an active level.
0111: PWM mode 2
- During up-counting, channel 2 has an inactive level when CNTR <
CH2CR or otherwise has an active level.
- During down-counting, channel 2 has an active level when CNTR >
CH2CR or otherwise has an inactive level.
1110: Asymmetric PWM mode 1
- During up-counting, channel 2 has an active level when CNTR < CH2CR or otherwise has an inactive level.
- During down-counting, channel 2 has an inactive level when CNTR >
CH2ACR or otherwise has an active level.
1111: Asymmetric PWM mode 2
- During up-counting, channel 2 has an inactive level when CNTR <
CH2CR or otherwise has an active level.
- During down-counting, channel 2 has an active level when CNTR >
CH2ACR or otherwise has an inactive level.
Note: When channel 2 is used as asymmetric PWM output mode, the Counter Mode
Selection bit in Counter Configuration Register must be configured as Centeraligned Counting mode (CMSEL = 0x1/0x2/0x3)
Rev. 1.00 503 of 637 December 28, 2020
32-Bit Arm ®
HT32F5828
Cortex ® -M0+ MCU
Channel 3 Output Configuration Register – CH3OCFR
This register specifies the channel 3 output mode configuration.
Offset: 0x04C
Reset value: 0x0000_0000
31
Type/Reset
Type/Reset
Type/Reset
Type/Reset
23
15
7
30
22
29
21
28
20
27
Reserved
19
Reserved
26
18
25
17
24
16
14 13 12 11
Reserved
6 5 4 3
Reserved CH3IMAE CH3PRE Reserved
RW 0 RW 0
10
2
9
1
CH3OM[2:0]
8
CH3OM[3]
RW 0
0
RW 0 RW 0 RW 0
Bits
[5]
[4]
Field Descriptions
CH3IMAE Channel 3 Immediate Active Enable
0: No action
1: Single pulse Immediate Active Mode is enabled
The CH3OREF signal will be forced to the compare matched level immediately after an available trigger event occurs irrespective of the result of the comparison between the CNTR and the CH3CR values.
The effective duration ends automatically at the next overflow or underflow event.
Note: The CH3IMAE bit is available only if the channel 3 is configured to be operated in the PWM mode 1 or PWM mode 2.
CH3PRE Channel 3 Compare Register (CH3CR) Preload Enable
0: CH3CR preload function is disabled.
The CH3CR register can be immediately assigned a new value when the
CH3PRE bit is cleared to 0 and the updated CH3CR value is used immediately.
1: CH3CR preload function is enabled
The new CH3CR value will not be transferred to its shadow register until the update event occurs.
Rev. 1.00 504 of 637 December 28, 2020
32-Bit Arm ®
HT32F5828
Cortex ® -M0+ MCU
Bits
[8][2:0]
Field Descriptions
CH3OM[3:0] Channel 3 Output Mode Setting
These bits define the functional types of the output reference signal CH3OREF.
0000: No Change
0001: Output 0 on compare match
0010: Output 1 on compare match
0011: Output toggles on compare match
0100: Force inactive – CH3OREF is forced to 0
0101: Force active – CH3OREF is forced to 1
0110: PWM mode 1
- During up-counting, channel 3 has an active level when CNTR < CH3CR or otherwise has an inactive level.
- During down-counting, channel 3 has an inactive level when CNTR >
CH3CR or otherwise has an active level.
0111: PWM mode 2
- During up-counting, channel 3 has an inactive level when CNTR <
CH3CR or otherwise has an active level.
- During down-counting, channel 3 has an active level when CNTR >
CH3CR or otherwise has an inactive level
1110: Asymmetric PWM mode 1
- During up-counting, channel 3 has an active level when CNTR < CH3CR or otherwise has an inactive level.
- During down-counting, channel 3 has an inactive level when CNTR >
CH3ACR or otherwise has an active level.
1111: Asymmetric PWM mode 2
- During up-counting, channel 3 has an inactive level when CNTR <
CH3CR or otherwise has an active level.
- During down-counting, channel 3 has an active level when CNTR >
CH3ACR or otherwise has an inactive level
Note: When channel 3 is used as asymmetric PWM output mode, the Counter Mode
Selection bit in Counter Configuration Register must be configured as Centeraligned Counting mode (CMSEL = 0x1/0x2/0x3)
Rev. 1.00 505 of 637 December 28, 2020
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