Register Descriptions. Holtek HT32F5828

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32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Register Descriptions

SCI Control Register – CR

This register contains the SCI control bits.

Offset: 0x000

Reset value: 0x0000_0000

31 30 29 28 27

Reserved

26 25 24

Type/Reset

23 22 21 20 19

Reserved

18 17 16

Type/Reset

15 14 13 12

Reserved

11 10 9

RXDMA

TXDMA

7 6

Reserved DETCNF

ENSCI

RETRY

SCIM

WTEN

RW 0 RW 0

CREP

CONV

RW 0 RW 0 RW 0 RW 0 RW 0 RW 0 RW 0

Bits

[9]

[8]

[6]

[5]

[4]

Field

RXDMA

TXDMA

DETCNF

ENSCI

RETRY

Descriptions

SCI reception DMA request enable

0: SCI reception DMA request is disabled

1: SCI reception DMA request is enabled

SCI transmission DMA request enable control

0: SCI transmission DMA request is disabled

1: SCI transmission DMA request is enabled

Card switch type selection

0: Switch is normally opened if no card is present

1: Switch is normally closed if no card is present

DETCNF

SCI_DET pin

STATUS

No card insert

Card insert

No card insert

This bit is set and cleared by the application program to configure the card detector switch type.

SCI finite state machine enable bit

0: SCI FSM is disabled and forced to its initial state

1: SCI FSM is enabled

Character transfer repetition time selection for a parity error condition

0: Data transfer 5 times when parity error occurs

1: Data transfer 4 times when parity error occurs

The bit is available only when the CREP bit is set to 1. When this bit is set to 1, the data will be transmitted or received 4 times once a parity error occurs. If the bit is cleared to 0, the data will be transferred 5 times if a parity error occurs.

Rev. 1.00 327 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Bits

[3]

[2]

[1]

[0]

Field

SCIM

WTEN

CREP

CONV

Descriptions

SCI Mode Selection

0: SCI data transfer in manual mode

1: SCI data transfer in SCI mode

This bit is set and cleared by the application program to select the SCI data Transfer

Mode. If it is cleared to 0, the SCI_DIO pin status is the same as the value of the

CDIO bit in the CCR register. If it is set to 1, the SCI_DIO pin is driven by the internal

SCI control circuitry. Before the data transfer type is switched from the Manual Mode to the SCI Mode, the CDIO bit must be set to 1 to avoid an SCI malfunction.

Waiting Time Counter enable control

0: Waiting Time Counter stops counting

1: Waiting Time Counter starts counting

The WTEN bit is set and cleared by the application program. When the WTEN bit is cleared to 0, a write access to the WTR register will load the value into the waiting time counter. If it is set to 1, the waiting time counter is enabled and automatically reloaded with the value at each start bit occurrence.

Automatic character repetition enable control for a parity error condition

0: No retry on parity error

1: Automatic retry on parity error

The CREP bit is set and cleared by the application program. When the CREP bit is cleared to 0, both the RXCF and PARF flags will be set when a parity error occurs in the reception mode after the data is received. However, in the Transmission Mode, the PARF flag will be set but the TXCF flag will not be set when a parity error occurs.

If the CREP bit is set to 1, a character transfer will automatically be activated 4 or 5 times depending upon the RETRY bit value. In the Transmission Mode the character will be re-transmitted if the transmitted data has a parity error. Here the parity error flag, PARF, will be set at the end of the 4 th or 5 th transmission without the TXCF bit being set. In the reception mode if the received data has a parity error, the SCI will inform the external Smart Card for 4 or 5 times and then the PARF and RXCF flags will both be set at the end of the 4 th or 5 th reception.

Data direction convention select

0: LSB is transferred first; a data “1” is a logic high level on the SCI_DIO pin and the parity bit is added after the MSB.

1: MSB is transferred first; a data “1” is a logic low level on the SCI_DIO pin and the parity bit is added after the LSB.

This bit is set and cleared by the application program to select if the data is transmitted LSB or MSB first. When the data direction convention is the same as the data direction specified by the external Smart Card, only the RXCF flag will be set to 1 without a parity error. Otherwise, both the RXCF and PARF flags will be set to 1 after the data is received.

Rev. 1.00 328 of 637 December 28, 2020