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32-Bit Arm ®
HT32F5828
Cortex ® -M0+ MCU
Bits
[7]
[5]
[0]
Field
CRCRST
USBRST
DMARST
Descriptions
CRC Reset Control
0: No reset
1: Reset CRC
This bit is set by software and cleared to 0 by hardware automatically.
USB Reset Control
0: No reset
1: Reset USB
This bit is set by software and cleared to 0 by hardware automatically.
Peripheral DMA (PDMA) Reset Control
0: No reset
1: Reset Peripheral DMA (PDMA)
This bit is set by software and cleared to 0 by hardware automatically.
APB Peripheral Reset Register 0 – APBPRSTR0
This register specifies several APB peripherals software reset control bits.
Offset: 0x108
Reset value: 0x0000_0000
Type/Reset
31
23
30
Reserved
22
29
21
28
20
27 26 25 24
SCI1RST Reserved I2SRST SCI0RST
RW 0
19
Reserved
18
RW 0 RW 0
17 16
Type/Reset
Type/Reset RW 0 RW 0
7 6 5 4
Reserved SPI1RST SPI0RST
Type/Reset
15 14
EXTIRST AFIORST
13 12 11 10 9 8
Reserved UR1RST UR0RST Reserved USRRST
RW 0 RW 0
RW 0 RW 0
3 2 1
RW 0
0
Reserved I2C1RST I2C0RST
RW 0 RW 0
Bits
[27]
[25]
[24]
Field
SCI1RST
I2SRST
SCI0RST
Descriptions
SCI1 Reset Control
0: No reset
1: Reset SCI1
This bit is set by software and cleared to 0 by hardware automatically.
I 2 S Reset Control
0: No reset
1: Reset I 2 S
This bit is set by software and cleared to 0 by hardware automatically.
SCI0 Reset Control
0: No reset
1: Reset SCI0
This bit is set by software and cleared to 0 by hardware automatically.
Rev. 1.00 73 of 637 December 28, 2020
32-Bit Arm ®
HT32F5828
Cortex ® -M0+ MCU
Bits
[15]
[1]
[0]
[5]
[4]
[14]
[11]
[10]
[8]
Field
EXTIRST
AFIORST
UR1RST
UR0RST
USRRST
SPI1RST
SPI0RST
I2C1RST
I2C0RST
Descriptions
External Interrupt Controller Reset Control
0: No reset
1: Reset EXTI
This bit is set by software and cleared to 0 by hardware automatically.
Alternate Function I/O Reset Control
0: No reset
1: Reset Alternate Function I/O
This bit is set by software and cleared to 0 by hardware automatically.
UART1 Reset Control
0: No reset
1: Reset UART1
This bit is set by software and cleared to 0 by hardware automatically.
UART0 Reset Control
0: No reset
1: Reset UART0
This bit is set by software and cleared to 0 by hardware automatically.
USART Reset Control
0: No reset
1: Reset USART
This bit is set by software and cleared to 0 by hardware automatically.
SPI1 Reset Control
0: No reset
1: Reset SPI1
This bit is set by software and cleared to 0 by hardware automatically.
SPI0 Reset Control
0: No reset
1: Reset SPI0
This bit is set by software and cleared to 0 by hardware automatically.
I 2 C1 Reset Control
0: No reset
1: Reset I 2 C1
This bit is set by software and cleared to 0 by hardware automatically.
I 2 C0 Reset Control
0: No reset
1: Reset I 2 C0
This bit is set by software and cleared to 0 by hardware automatically.
Rev. 1.00 74 of 637 December 28, 2020
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