Timer PDMA/Interrupt Control Register – DICTR. Holtek HT32F5828

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Bits

[2]

[0]

Field

CH1P

CH0P

Descriptions

Channel 1 Capture/Compare Polarity

- When Channel 1 is configured as an input (CH1CCS = 0x1/0x2/0x3)

0: capture event occurs on a Channel 1 rising edge

1: capture event occurs on a Channel 1 falling edge

- Channel 1 is configured as an output (CH1CCS = 0x0)

0: Channel 1 Output is active high

1: Channel 1 Output is active low

Channel 0 Capture/Compare Polarity

- When Channel 0 is configured as an input (CH0CCS = 0x1/0x2/0x3)

0: capture event occurs on a Channel 0 rising edge

1: capture event occurs on a Channel 0 falling edge

- When Channel 0 is configured as an output (CH0CCS = 0x0)

0: Channel 0 Output is active high

1: Channel 0 Output is active low

Timer PDMA/Interrupt Control Register – DICTR

This register contains the timer PDMA and interrupt enable control bits.

Offset: 0x074

Reset value: 0x0000_0000

Type/Reset

Type/Reset

Type/Reset

Type/Reset

31

23

15

7

30

22

14

6

29

Reserved

21

Reserved

13

Reserved

5

Reserved

28

20

12

4

27 26 25 24

TEVDE Reserved UEVDE

19

RW 0

18 17

RW 0

16

CH3CCDE CH2CCDE CH1CCDE CH0CCDE

RW 0 RW 0 RW 0 RW 0

11 10 9 8

TEVIE

RW 0

Reserved UEVIE

RW 0

3 2 1 0

CH3CCIE CH2CCIE CH1CCIE CH0CCIE

RW 0 RW 0 RW 0 RW 0

Bits

[26]

[24]

[19]

[18]

Field Descriptions

TEVDE

UEVDE

Trigger event PDMA Request Enable

0: Trigger PDMA request is disabled

1: Trigger PDMA request is enabled

Update event PDMA Request Enable

0: Update event PDMA request is disabled

1: Update event PDMA request is enabled

CH3CCDE Channel 3 Capture/Compare PDMA Request Enable

0: Channel 3 PDMA request is disabled

1: Channel 3 PDMA request is enabled

CH2CCDE Channel 2 Capture/Compare PDMA Request Enable

0: Channel 2 PDMA request is disabled

1: Channel 2 PDMA request is enabled

Rev. 1.00 456 of 637 December 28, 2020

32-Bit Arm ®

HT32F5828

Cortex ® -M0+ MCU

Bits

[17]

[2]

[1]

[0]

[8]

[3]

[16]

[10]

Field Descriptions

CH1CCDE Channel 1 Capture/Compare PDMA Request Enable

0: Channel 1 PDMA request is disabled

1: Channel 1 PDMA request is enabled

CH0CCDE Channel 0 Capture/Compare PDMA Request Enable

0: Channel 0 PDMA request is disabled

1: Channel 0 PDMA request is enabled

TEVIE Trigger event Interrupt Enable

0: Trigger event interrupt is disabled

1: Trigger event interrupt is enabled

UEVIE

CH3CCIE

Update event Interrupt Enable

0: Update event interrupt is disabled

1: Update event interrupt is enabled

Channel 3 Capture/Compare Interrupt Enable

0: Channel 3 interrupt is disabled

1: Channel 3 interrupt is enabled

CH2CCIE

CH1CCIE

CH0CCIE

Channel 2 Capture/Compare Interrupt Enable

0: Channel 2 interrupt is disabled

1: Channel 2 interrupt is enabled

Channel 1 Capture/Compare Interrupt Enable

0: Channel 1 interrupt is disabled

1: Channel 1 interrupt is enabled

Channel 0 Capture/Compare Interrupt Enable

0: Channel 0 interrupt is disabled

1: Channel 0 interrupt is enabled

Rev. 1.00 457 of 637 December 28, 2020