advertisement
32-Bit Arm ®
HT32F5828
Cortex ® -M0+ MCU
Clock Controller
The following describes the Timer Module clock controller which determines the clock source of the internal prescaler counter.
▆
Internal APB clock f
CLKIN
The default internal clock source is the APB clock f
0x6, the internal APB clock f
CLKIN
CLKIN
used to drive the counter prescaler when the slave mode is disabled. When the slave mode selection bits SMSEL are set to 0x4, 0x5 or
is the counter prescaler driving clock source. If the slave mode controller is enabled by setting SMSEL field in the MDCFR register to 0x7, the prescaler is clocked by other clock sources selected by the TRSEL field in the TRCFR register and described as follows.
▆
STIED
The counter prescaler can count during each rising edge of the STI signal. This mode can be selected by setting the SMSEL field to 0x7 in the MDCFR register. Here the counter will act as an event counter. The input event, known as STI here, can be selected by setting the TRSEL field to an available value except the value of 0x0. When the STI signal is selected as the clock source, the internal edge detection circuitry will generate a clock pulse during each STI signal rising edge to drive the counter prescaler. It is important to note that if the TRSEL field is set to
0x0 to select the software UEVG bit as the trigger source, then when the SMSEL field is set to
0x7, the counter will be updated instead of counting.
PSCR CRR
Update Event f
CLKIN
(Internal APB clock)
STIED
(Trigger events)
CK_PSC
CLK
PSC Prescaler
Reset
CK_CNT
CLK
CNTR
Reset
TM_CNT
TRSEL
SMSEL
Start/Stop
Figure 176. SCTM Clock Source Selection
Overflow
UEVG bit
Slave Restart mode trigger
Rev. 1.00 520 of 637 December 28, 2020
32-Bit Arm ®
HT32F5828
Cortex ® -M0+ MCU
Trigger Controller
The trigger controller is used to select the trigger source and setup the trigger level or edge trigger condition. For the internal trigger input, it can be selected by the Trigger Selection bits TRSEL in the TRCFR register. For all the trigger sources except the UEVG bit software trigger, the internal edge detection circuitry will generate a clock pulse at each trigger signal rising edge to stimulate some SCTM functions which are triggered by a trigger signal rising edge.
Edge Trigger Source = Channel input
Edge Trigger Mux
0
TISED
TIBED
Reserved
Reserved
Reserved
Reserved
000
001
010
011 others
Reserved
Reserved
Reserved
TRSEL[2:0]
STIED_S1
000
001
010
011 others STIED_S0
0
1
TRSEL[3]
STIED
Level Trigger Source = Channel input + Software UEVG bit
S/W Set
UEVG Bit
TIS
Level Trigger Mux
TRSEL[2:0]
Reserved
Reserved
Reserved
0
Reserved
Reserved
Reserved
Reserved
000
001
010
011 others
STI_S1
000
001
010
011 others
STI_S0
0
1
TRSEL[3]
Figure 177. Trigger Controller Block
STI
Rev. 1.00 521 of 637 December 28, 2020
32-Bit Arm ®
HT32F5828
Cortex ® -M0+ MCU
Slave Controller
The SCTM can be synchronized with an external trigger in several modes including the Restart mode, the Pause mode and the Trigger mode which is selected by the SMSEL field in the MDCFR register. The trigger input of these modes comes from the STI signal which is selected by the
TRSEL field in the TRCFR register. The operation modes in the Slave Controller are described in the accompanying sections.
Trigger Controller
STI
Slave
Controller
SMSEL
Trigger Event
Reset/Stop/Start Counter
Restart/Pause/Trigger Mode
Figure 178. Slave Controller Diagram
Restart Mode
The counter and its prescaler can be reinitialized in response to a rising edge of the STI signal.
When an STI rising edge occurs, the update event software generation bit named UEVG will automatically be asserted by hardware and the trigger event flag will also be set. Then the counter and prescaler will be reinitialized. Although the UEVG bit is set to 1 by hardware, the update event does not really occur. It depends upon whether the update event disable control bit UEVDIS is set to 1 or not. If the UEVDIS is set to 1 to disable the update event to occur, there will no update event be generated, however the counter and prescaler are still reinitialized when the STI rising edge occurs. If the UEVDIS bit in the CNTCFR register is cleared to enable the update event to occur, an update event will be generated together with the STI rising edge, then all the preloaded registers will be updated.
Timer Counter Reload Register CRR = 32
STI source signal
(polarity=0)
STI source signal
(polarity=1)
STI
CK_CNT
UEVG bit
(reset counter)
CNTR
(Up-counting)
TEVIF
27 28 29
Figure 179. SCTM in Restart Mode
Sync.
30 31
Trigger Event
0 1 2
Rev. 1.00 522 of 637 December 28, 2020
32-Bit Arm ®
HT32F5828
Cortex ® -M0+ MCU
Pause Mode
In the Pause Mode, the selected STI input signal level is used to control the counter start/stop operation. The counter starts to count when the selected STI signal is at a high level and stops counting when the STI signal is changed to a low level, here the counter will maintain its present value and will not be reset. Since the Pause function depends upon the STI level to control the counter stop/start operation, the selected STI trigger signal can not be derived from the TIBED signal.
STI source signal
(polarity=0)
STI source signal
(polarity=1)
STI
CK_ CNT
CNT_ EN
CNTR
TEVIF
Sync
27 28 29
Sync
30 31
Software clearing
Figure 180. SCTM in Pause Mode
Trigger Mode
After the counter is disabled to count, the counter can resume counting when an STI rising edge signal occurs. When an STI rising edge occurs, the counter will start to count from the current value in the counter. Note that if the STI signal is selected to be derived from the UEVG bit software trigger, the counter will not resume counting. When software triggering using the UEVG bit is selected as the STI source signal, there will be no clock pulse generated which can be used to make the counter resume counting. Note that the STI signal is only used to enable the counter to resume counting and has no effect on controlling the counter to stop counting.
STI source signal
(polarity=0)
STI source signal
(polarity=1)
STI
CK_CNT
CNT_EN
CNTR
(Up-counting)
TEVIF
27
Sync
28 29 30 31 32
Software clearing
Figure 181. SCTM in Trigger Mode
Rev. 1.00 523 of 637 December 28, 2020
32-Bit Arm ®
HT32F5828
Cortex ® -M0+ MCU
Channel Controller
The SCTM channel can be used as the capture input or compare match output. The capture input or compare match output channel is composed of a preload register and a shadow register. Data access of the APB bus is always implemented by reading/writing the preload register.
When used in the input capture mode, the counter value is captured into the CHCCR shadow register first and then transferred into the CHCCR preload register when the capture event occurs.
When used in the compare match output mode, the contents of the CHCCR preload register is copied into the associated shadow register; the counter value is then compared with the register value.
APB Bus Interface
CHPSC
Read CHCCR
Capture
Controller
CHCCS
CHCCG
CHE
Capture Transfer
CHCCR
(Preload Register)
Compare Transfer
Compare
Controller
CHCCR
(Shadow Register)
Capture
CHCCS
CHPRE
CHCCR
TM_CNT
Figure 182. Capture/Compare Block Diagram
Write CHCCR
Update Event
Rev. 1.00 524 of 637 December 28, 2020
32-Bit Arm ®
HT32F5828
Cortex ® -M0+ MCU
Capture Counter Value Transferred to CHCCR
When the channel is used as a capture input, the counter value is captured into the Channel
Capture/Compare Register (CHCCR) when an effective input signal transition occurs. Once the capture event occurs, the CHCCIF flag in the INTSR register is set accordingly. If the CHCCIF bit is already set, i.e., the flag has not yet been cleared by software, and another capture event on this channel occurs, the corresponding channel Over-Capture flag, named CHOCF, will be set.
f
CLKIN
SCTM_CH
CNTR 25
CHCCR 0
26
CHCCIF
CHOCF
Figure 183. Input Capture Mode
27 28
26
29 30 31 32 33 34 35
32
Rev. 1.00 525 of 637 December 28, 2020
32-Bit Arm ®
HT32F5828
Cortex ® -M0+ MCU
Input Stage
The input stage consists of a digital filter, a channel polarity selection, edge detection and a channel prescaler. The channel input signal (TI) is sampled by a digital filter to generate a filtered input signal TIFP. Then the channel polarity and the edge detection block can generate a TISED signal for the input capture function. The effective input event number can be set by the channel capture input source prescaler setting field (CHPSC).
f
CLKIN
Edge
Detection
Edge
Detection
CHCCS
TIBED
SCTM_CH
TI f sampling
Filter
TIFP TIFN
TIF
Figure 184. Channel Input Stages f
CLKIN
TIS
CHP
Edge
Detection
TISED
CH
PRESCALER
CHPSC
CHPSC
CHCAP Event
Digital Filter
The digital filter is embedded in the channel input stage. The digital filter in the SCTM is an N-event counter where N refers to how many valid transitions are necessary to output a filtered signal. The
N value can be 0, 2, 4, 5, 6 or 8 according to the user selection for this digital filter.
No Filtered
Digital Filter (N=2)
TI
D Q D Q D Q f
SYSTEM
CK CK f sampling
CK
Figure 185. TI Digital Filter Diagram with N = 2
J
CK
Q
K
Filtered
Rev. 1.00 526 of 637 December 28, 2020
advertisement
Related manuals
advertisement