About this document PM0253 order superscalar processor delivers exceptional power efficiency through an efficient instruction set and extensively optimized design, providing high-end processing hardware including IEEE754-compliant single-precision and double-precision floating-point computation, a range of single-cycle and SIMD multiplication and multiply-with-accumulate capabilities, saturating arithmetic and dedicated hardware division.
To facilitate the design of cost-sensitive devices, the Cortex ® -M7 processor implements tightly-coupled system components that reduce processor area while significantly improving interrupt handling and system debug capabilities. The Cortex ® -M7 processor implements a version of the Thumb
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instruction set based on Thumb-2 technology, ensuring high code density and reduced program memory requirements. The Cortex ® -M7 instruction set provides the exceptional performance expected of a modern 32-bit architecture, with the high code density of 8-bit and 16-bit microcontrollers.
The Cortex ® -M7 processor closely integrates a configurable NVIC, to deliver industryleading interrupt performance. The NVIC includes a Non Maskable Interrupt (NMI), and provides up to 256 interrupt priority levels. The tight integration of the processor core and
NVIC provides fast execution of interrupt service routines (ISRs), dramatically reducing the interrupt latency. This is achieved through the hardware stacking of registers, and the ability to suspend load-multiple and store-multiple operations. Interrupt handlers do not require wrapping in assembler code, removing any code overhead from the ISRs. A tail-chain optimization also significantly reduces the overhead when switching from one ISR to another.
To optimize low-power designs, the NVIC integrates with the sleep modes, that include a deep sleep function that enables the entire device to be rapidly powered down while still retaining program state.
The reliability is increased with automatic fault detection and handling built-in. The
Cortex ® -M7 processor uses ECC and SECDED on accesses to memory and has Memory
Build-in Self Test (MBIST) capability. The Cortex ® -M7 processor is dual-redundant, which means it can operate in lock-step. The MCU vendor determines the reliability features configuration and therefore this can differ across different devices and families.
To increase instruction throughput, the Cortex ® -M7 processor can execute certain pairs of instructions simultaneously. This is called dual issue.
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The Cortex
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-M7 processor provides multiple interfaces using AMBA
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technology to provide high speed, low latency memory accesses. It supports unaligned data accesses.
The Cortex
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-M7 processor has an MPU that provides fine grain memory control, enabling applications to utilize multiple privilege levels, separating and protecting code, data and stack on a task-by-task basis. Such requirements are becoming critical in many embedded applications such as automotive.
Integrated configurable debug
The Cortex ® -M7 processor implements a complete hardware debug solution. This provides high system visibility of the processor and memory through either a traditional JTAG port or a 2-pin Serial Wire Debug (SWD) port that is ideal for microcontrollers and other small package devices. The MCU vendor determines the debug feature configuration and therefore this can differ across different devices and families.
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