Access control. STMicroelectronics STM32H7S3L8, STM32H7R3L8, STM32H7S7A8, STM32H7R3V8, STM32H7R3R8, STM32H7S3Z8, STM32H7S3I8, STM32H7S3V8, STM32H7S7Z8, STM32H7R7I8

PM0253 Cortex-M7 peripherals

STR <inst_address1>, DCCMVAU ; Clean data cache by MVA to point of

; unification (PoU).

STR <inst_address1>, ICIMVAU ; Invalidate instruction cache by MVA to

; PoU.

DSB ; Ensure completion of the invalidations.

ISB ; Synchronize fetched instruction stream.

Control of the L1-cache ECC and attribute override, the priority of AHB slave traffic, and whether an access is mapped to TCM interfaces or AXI master interface, is defined by the access control registers. The access control registers are:

Address

Table 104. Access control register summary

Name Type

Required privilege

Reset value

Description

0xE000EF90 ITCMCR RW Privileged 0x00000000

0xE000EF94 DTCMCR RW Privileged 0x00000000

Instruction and data tightly-coupled memory control registers on page 246

0xE000EF98 AHBPCR RW Privileged 0x00000000

AHBP control register on page 248

0xE000EF9C CACR RW Privileged -

(1)

Auxiliary cache control register on page 249

0xE000EFA0 AHBSCR RW Privileged 0x00000800

AHB slave control register on page 250

0xE000EFA8 ABFSR RW Privileged 0x00000000

Auxiliary bus fault status register on page 251

1. The reset value is implementation and configuration dependent and the silicon vendor changes this. If cache ECC is configured the reset value is 0x00000000, if cache ECC is not configured the reset value is 0x00000002.

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