CMSIS functions. STMicroelectronics STM32H7S3L8, STM32H7R3L8, STM32H7S7A8, STM32H7R3V8, STM32H7R3R8, STM32H7S3Z8, STM32H7S3I8, STM32H7S3V8, STM32H7S7Z8, STM32H7R7I8

The Cortex-M7 instruction set PM0253

To ensure a smooth transition, Arm recommends that the code designed to operate on other

Cortex ® -M profile processor architectures obey the following rules and that the

Configuration and Control Register (CCR) be appropriately configured:

• Use word transfers only to access registers in the NVIC and System Control Space

(SCS).

• Treat all unused SCS registers and register fields on the processor as Do-Not-Modify.

• Configure the following fields in the CCR register:

– STKALIGN bit to 1.

– UNALIGN_TRP bit to 1.

– Leave all other bits in the CCR register at their original value.

ISO/IEC C code cannot directly access some Cortex

®

-M7 processor instructions. This section describes intrinsic functions that can generate these instructions, provided by the

CMSIS and that might be provided by a C compiler. If a C compiler does not support an appropriate intrinsic function, the user might have to use inline assembler to access some instructions.

The CMSIS provides the following intrinsic functions to generate instructions that ISO/IEC C code cannot directly access:

Table 24. CMSIS functions to generate some Cortex

®

-M7 processor instructions

Instruction CMSIS function

CPSIE I

CPSID I

CPSIE F

CPSID F

ISB

DSB

DMB

REV

REV16

REVSH

RBIT

SEV

WFE

WFI void __enable_irq(void) void __disable_irq(void) void __enable_fault_irq(void) void __disable_fault_irq(void) void __ISB(void) void __DSB(void) void __DMB(void) uint32_t __REV(uint32_t int value) uint32_t __REV16(uint32_t int value) uint32_t __REVSH(uint32_t int value) uint32_t __RBIT(uint32_t int value) void __SEV(void) void __WFE(void) void __WFI(void)

The CMSIS also provides a number of functions for accessing the special registers using

MRS and MSR instructions:

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