Cortex-M7 peripherals. STMicroelectronics STM32H7S3L8, STM32H7R3L8, STM32H7S7A8, STM32H7R3V8, STM32H7R3R8, STM32H7S3Z8, STM32H7S3I8, STM32H7S3V8, STM32H7S7Z8, STM32H7R7I8

PM0253 Cortex-M7 peripherals

4.1 About the Cortex-M7 peripherals

The address map of the Private peripheral bus (PPB) is:

Address

Table 39. Core peripheral register regions

Core peripheral

0xE000E008-0xE000E00F

0xE000E010-0xE000E01F

0xE000E100-0xE000E4EF

System control block

System timer

Nested Vectored Interrupt Controller

0xE000ED00-0xE000ED3F System control block

0xE000ED78- 0xE000ED84 Processor features

0xE000ED90-0xE000EDB8 Memory Protection Unit

0xE000EF00-0xE000EF03

0xE000EF30-0xE000EF44

0xE000EF50-0xE000EF78

0xE000EF90-0xE000EFA8

Nested Vectored Interrupt Controller

Floating-Point Unit

Cache maintenance operations

Access control

Description

Table 50 on page 192

Table 71 on page 213

Table 40 on page 184

Table 50 on page 192

Table 77 on page 217

Table 84 on page 222

Table 40 on page 184

Table 94 on page 233

Table 100 on page 240

Table 104 on page 245

In the register descriptions:

• the register type is described as follows:

RW Read and write.

RO

WO

Read-only.

Write-only.

• the required privilege gives the privilege level required to access the register, as follows:

Privileged

Only privileged software can access the register.

Unprivileged

Both unprivileged and privileged software can access the register.

Attempting to access a privileged register from unprivileged software results in a BusFault.

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