System control block. STMicroelectronics STM32H7S3L8, STM32H7R3L8, STM32H7S7A8, STM32H7R3V8, STM32H7R3R8, STM32H7S3Z8, STM32H7S3I8, STM32H7S3V8, STM32H7S7Z8, STM32H7R7I8

Cortex-M7 peripherals PM0253

The System Control Block (SCB) provides system implementation information, and system control. This includes configuration, control, and reporting of the system exceptions. The system control block registers are:

Address

Table 50. Summary of the system control block registers

Name Type

Required privilege

Reset value

Description

0xE000E008

0xE000ED00

0xE000ED04

0xE000ED08

0xE000ED34

0xE000ED38

ACTLR

CPUID

ICSR

VTOR

0xE000ED0C AIRCR

0xE000ED10

0xE000ED20

0xE000ED24

SCR

0xE000ED14 CCR

SHPR3

SHCRS

0xE000ED28 CFSR

0xE000ED28 MMSR (2)

0xE000ED29 BFSR

(2)

0xE000ED2A UFSR

(2)

0xE000ED2C HFSR

MMAR

BFAR

0xE000ED3C AFSR

RW

RO

RW (1)

RW

RW

RW

RW

0xE000ED18 SHPR1 RW

0xE000ED1C SHPR2 RW

RW

RW

(1)

Privileged 0x00000000

Auxiliary control register on page 193

Privileged 0x410FC270

CPUID base register on page 194

Privileged 0x00000000

Interrupt control and state register on page 194

Privileged Unknown

Privileged 0xFA050000

Vector table offset register on page 197

Application interrupt and reset control register on page 197

Privileged 0x00000000

System control register on page 199

Privileged 0x00000200

Configuration and control register on page 200

Privileged 0x00000000

System handler priority register 1 on page 202

Privileged 0x00000000

System handler priority register 2 on page 203

Privileged 0x00000000

System handler priority register 3 on page 203

Privileged 0x00000000

System handler control and state register on page 204

RW

RW

RW

Privileged 0x00000000

Configurable fault status register on page 205

Privileged 0x00

MemManage fault address register on page 211

Privileged 0x00

BusFault status register on page 207

RW

RW

RW

Privileged 0x0000

Privileged 0x00000000

Privileged Unknown

RW Privileged Unknown

RAZ/WI Privileged -

Auxiliary control register on page 193

HardFault status register on page 210

MemManage fault address register on page 211

BusFault address register on page 212

Auxiliary Fault Status register not implemented

1. See the register description for more information.

2. A subregister of the CFSR.

192/254 PM0253 Rev 5