System handler control and state register. STMicroelectronics STM32H7S3L8, STM32H7R3L8, STM32H7S7A8, STM32H7R3V8, STM32H7R3R8, STM32H7S3Z8, STM32H7S3I8, STM32H7S3V8, STM32H7S7Z8, STM32H7R7I8

Cortex-M7 peripherals

4.3.9 System handler control and state register

PM0253

The SHCSR enables the system handlers, and indicates:

• The pending status of the BusFault, MemManage fault, and SVC exceptions.

• The active status of the system handlers.

See the register summary in

Table 50 on page 192

for the SHCSR attributes. The bit assignments are:

31

Reserved

Figure 34. SHCSR bit assignments

19 18 17 16 15 14 13 12 11 10 9 8 7 6 4 3 2 1 0

USGFAULTENA

BUSFAULTENA

MEMFAULTENA

SVCALLPENDED

BUSFAULTPENDED

MEMFAULTPENDED

USGFAULTPENDED

SYSTICKACT

PENDSVACT

Reserved

MONITORACT

SVCALLACT

MEMFAULTACT

BUSFAULTACT

Reserved

USGFAULTACT

Reserved

MSv39688V1

[11]

[10]

[9]

[8]

[7]

[6:4]

[3]

Bits Name

[31:19] -

[18]

[17]

USGFAULTENA

BUSFAULTENA

[16]

[15]

MEMFAULTENA

SVCALLPENDED

[14]

[13]

[12]

BUSFAULTPENDED

USGFAULTPENDED

SYSTICKACT

PENDSVACT

-

MONITORACT

-

SVCALLACT

USGFAULTACT

Table 63. SHCSR bit assignments

Function

MEMFAULTPENDED

Reserved

UsageFault enable bit, set to 1 to enable

(1)

BusFault enable bit, set to 1 to enable

(1)

MemManage enable bit, set to 1 to enable

(1)

SVCall pending bit, reads as 1 if exception is pending

(2)

BusFault exception pending bit, reads as 1 if exception is

pending

(2)

MemManage exception pending bit, reads as 1 if exception is

pending

(2)

UsageFault exception pending bit, reads as 1 if exception is

pending

(2)

SysTick exception active bit, reads as 1 if exception is active

(3)

PendSV exception active bit, reads as 1 if exception is active

Reserved

Debug monitor active bit, reads as 1 if Debug monitor is active

SVCall active bit, reads as 1 if SVC call is active

Reserved

UsageFault exception active bit, reads as 1 if exception is active

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