System control register. STMicroelectronics STM32H7S3L8, STM32H7R3L8, STM32H7S7A8, STM32H7R3V8, STM32H7R3R8, STM32H7S3Z8, STM32H7S3I8, STM32H7S3V8, STM32H7S7Z8, STM32H7R7I8

PM0253

Note:

4.3.6

Cortex-M7 peripherals

Table 56. Priority grouping (continued)

Interrupt priority level value, PRI_ N [7:0] Number of

PRIGROUP Binary point

(1)

Group priority bits

Subpriority bits

Group priorities

Subpriorities

0b101

0b110

0b111 bxx.yyyyyy

bx.yyyyyyy

b.yyyyyyyy

[7:6]

[7]

None

[5:0]

[6:0]

[7:0]

4

2

1

64

128

256

1. PRI_ n [7:0] field showing the binary point. x denotes a group priority field bit, and y denotes a subpriority field bit.

Determining preemption of an exception uses only the group priority field, see Interrupt priority grouping on page 43 .

System control register

The SCR controls features of entry to and exit from Low-power state. See the register summary in

Table 50 on page 192

for its attributes. The bit assignments are

Figure 29. SCR bit assignments:

31 5 4 3 2 1 0

Reserved

Bits

[31:5] -

[4]

[3] -

Name

SEVONPEND

SEVONPEND

Reserved

SLEEPDEEP

SLEEPONEXIT

Reserved

MSv39687V1

Table 57. SCR bit assignments

Function

Reserved.

Send Event on Pending bit:

0: Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded.

1: Enabled events and all interrupts, including disabled interrupts, can wakeup the processor.

When an event or interrupt enters pending state, the event signal wakes up the processor from WFE. If the processor is not waiting for an event, the event is registered and affects the next WFE.

The processor also wakes up on execution of an SEV instruction or an external event.

Reserved.

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