Exception handlers. STMicroelectronics STM32H7S3L8, STM32H7R3L8, STM32H7S7A8, STM32H7R3V8, STM32H7R3R8, STM32H7S3Z8, STM32H7S3I8, STM32H7S3V8, STM32H7S7Z8, STM32H7R7I8

PM0253 The Cortex-M7 processor

Table 19. Properties of the different exception types (continued)

Exception number

(1)

IRQ number

(1)

Exception type

Priority

Vector address

(2)

Activation

15

15 -

-1 SysTick

Reserved -

Configurable

(3)

-

0x0000003C Asynchronous

-

16 and above

0 and above

Interrupt (IRQ) Configurable

(4)

0x00000040 and above (5)

Asynchronous

1. To simplify the software layer, the CMSIS only uses IRQ numbers. It uses negative values for exceptions

other than interrupts. The IPSR returns the Exception number, see Interrupt program status register on page 23

2. See

Figure 10: Vector table on page 42

for more information.

3. See

System handler priority registers on page 202 .

4. See

Interrupt priority registers on page 188

5. Increasing in step of 4.

For an asynchronous exception, other than reset, the processor can execute additional instructions between when the exception is triggered and when the processor enters the exception handler.

Privileged software can disable the exceptions that

Table 19 on page 40

shows as having configurable priority, see:

•

System handler control and state register on page 204

•

Interrupt clear-enable registers on page 186

.

For more information about HardFaults, MemManage faults, BusFaults, and UsageFaults,

see Section 2.5: Fault handling on page 47

The processor handles exceptions using:

Interrupt Service Routines (ISRs) Interrupts IRQ0 to IRQ239 are the exceptions handled by ISRs

Fault handler

System handlers

HardFault, MemManage fault, UsageFault, and

BusFault are fault exceptions handled by the fault handler.s

NMI, PendSV, SVCall SysTick, and the fault exceptions are all system exceptions handled by system handlers.

PM0253 Rev 5 41/254

51