Cortex-M7 peripherals PM0253
4.8.4 Cortex
®
-M7 cache maintenance operations using CMSIS
CMSIS functions enable the software portability between different Cortex ® -M profile processors. To access cache maintenance operations when using CMSIS, use the following functions:
Table 103. CMSIS access cache maintenance operations
CMSIS function Descriptions void SCB_EnableICache(void) void SCB_DisableICache(void) void SCB_InvalidateICache(void) void SCB_EnableDCache(void) void SCB_DisableDCache(void)
Invalidate and then enable instruction cache
Disable instruction cache and invalidate its contents
Invalidate instruction cache
Invalidate and then enable data cache
Disable data cache and then clean and invalidate its contents void SCB_InvalidateDCache(void)
Invalidate data cache
Clean data cache void SCB_CleanDCache(void) void SCB_CleanInvlaidateDCache(void)
Clean and invalidate data cache
4.8.5 Initializing and enabling the L1-cache
The user can use cache maintenance operations for:
• Cache startup type operations.
• Manipulating the caches so that shared data is visible to other bus masters.
• Enabling data changed by an external DMA agent to be made visible to the Cortex ®
M7 processor.
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After enabling or disabling the instruction cache, the user must issue an ISB instruction to flush the pipeline. This ensures that all subsequent instruction fetches see the effect of enabling or disabling the instruction cache.
After reset, the user must invalidate each cache before enabling it.
When disabling the data cache, the user must clean the entire cache to ensure that any dirty data is flushed to external memory.
Before enabling the data cache, the user must invalidate the entire data cache if external memory might have changed since the cache was disabled.
Before enabling the instruction cache, the user must invalidate the entire instruction cache if external memory might have changed since the cache was disabled.
L1 data and instruction cache must be invalidated before they are enabled in the software, otherwise unpredictable behavior can occur.
Invalidate the entire data cache
The software can use the following code example to invalidate the entire data cache, if it has been included in the processor. The operation is carried out by iterating over each line of the cache and using the DCISW register in the Private Peripheral Bus (PPB) memory region to
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PM0253 Cortex-M7 peripherals invalidate the line. The number of cache ways and sets is determined by reading the
CCSIDR register.
CCSIDR EQU 0xE000ED80
CSSELR EQU 0xE000ED84
DCISW EQU 0xE000EF60
MOV r0, #0x0
LDR r11, =CSSELR
STR r0, [r11] ; Select Data Cache size
DSB
LDR r11, =CCSIDR
LDR r2, [r11] ; Cache size identification
AND r1, r2, #0x7 ; Number of words in a cache line
ADD r7, r1, #0x4
MOV r1, #0x3ff
ANDS r4, r1, r2, LSR #3
MOV r1, #0x7fff
ANDS r2, r1, r2, LSR #13
CLZ r6, r4
LDR r11, =DCISW inv_loop1
MOV r1, r4 inv_loop2
LSL r3, r1, r6
LSL r8, r2, r7
ORRr 3, r3, r8
STR r3, [r11] ; Invalidate D-cache line
SUBS r1, r1, #0x1
BGE inv_loop2
SUBS r2, r2, #0x1
BGE inv_loop1
DSB
ISB
Invalidate instruction cache
The user can use the following code example to invalidate the entire instruction cache, if it has been included in the processor. The operation is carried out by writing to the ICIALLU register in the PPB memory region.
ICIALLU EQU 0xE000EF50
MOV r0, #0x0
LDR r11, =ICIALLU
STR r0, [r11]
DSB
ISB
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