Auxiliary cache control register. STMicroelectronics STM32H7S3L8, STM32H7R3L8, STM32H7S7A8, STM32H7R3V8, STM32H7R3R8, STM32H7S3Z8, STM32H7S3I8, STM32H7S3V8, STM32H7S7Z8, STM32H7R7I8

PM0253 Cortex-M7 peripherals

4.9.3 Auxiliary cache control register

The CACR controls the L1-cache ECC and attribute override. The bit assignments are:

Figure 62. CACR bit assignments

31 3 2 1 0

Reserved

FORCEWT

ECCEN

SIWT

MSv39655V1

Bits

[31:3] -

Name

[2]

[1]

[0]

-

Table 107. CACR bit assignments

Type Function

FORCEWT RW

ECCEN

SIWT

RW

RW

Reserved, RAZ/WI.

Enables Force Write-through in the data cache:

0: Disables Force Write-Through.

1: Enables Force Write-Through. Cacheable Write-Back memory regions are treated as Write-Through.

This bit is RAZ if the data cache is excluded.

Enables ECC in the instruction and data cache:

0: Enables ECC in the instruction and data cache.

1: Disables ECC in the instruction and data cache.

This bit is WI if both data cache and instruction cache are excluded or if ECC is not configured. If ECC is included in the processor the reset value of ECCEN is 0. If ECC is excluded the reset value of ECCEN is 1

Enables cache coherency usage:

0: Normal Cacheable Shared locations are treated as being Non-cacheable.

Programmed inner cacheability attributes are ignored. This is the default mode of operation for Shared memory. Caches are transparent to software for these locations and therefore no software maintenance is required to maintain coherency.

1: For the data cache, Normal Cacheable shared locations are treated as Writethrough. For the instruction cache, shared locations are treated as being Noncacheable. Programmed inner cacheability attributes are ignored. All writes are globally visible. Other memory agent updates are not visible to Cortex

®

-M7 software without suitable cache maintenance.

Useful for heterogeneous MP-systems where, for example, Cortex

®

-M7 processor is integrated on the Accelerator Coherency Port (ACP) interface on an MP-capable processor.

This bit is RAZ if the data cache is excluded.

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