Vector table. STMicroelectronics STM32H7S3L8, STM32H7R3L8, STM32H7S7A8, STM32H7R3V8, STM32H7R3R8, STM32H7S3Z8, STM32H7S3I8, STM32H7S3V8, STM32H7S7Z8, STM32H7R7I8

The Cortex-M7 processor PM0253

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The vector table contains the reset value of the stack pointer, and the start addresses, also

called exception vectors, for all exception handlers. Figure 10 on page 42 shows the order

of the exception vectors in the vector table. The least-significant bit of each vector must be

1, indicating that the exception handler is Thumb code, see Thumb state on page 25

.

Figure 10. Vector table

Exception number IRQ number Offset Vector

255

.

.

.

9

8

7

6

13

12

11

10

5

4

3

2

1

18

17

16

15

14

239

2

1

0

-1

-2

-5

-10

-11

-12

-13

-14

0x03FC

.

.

.

0x004C

0x0048

0x0044

0x0040

0x003C

0x0038

0x002C

IRQ239

.

.

.

IRQ2

IRQ1

IRQ0

Systick

PendSV

Reserved

Reserved for Debug

SVCall

Reserved

0x0018

0x0014

0x0010

0x000C

0x0008

0x0004

0x0000

Usage fault

Bus fault

Memory management fault

Hard fault

NMI

Reset

Initial SP value

MSv39645V1

On system reset, the vector table is at address 0x00000000. Privileged software can write to the VTOR to relocate the vector table start address to a different memory location, in the range 0x00000000 to 0xFFFFFF80.

The silicon vendor must configure the top range value, which is dependent on the number of interrupts implemented. The minimum alignment is 32 words, enough for up to 16 interrupts.

For more interrupts, adjust the alignment by rounding up to the next power of two. For example, if the user requires 21 interrupts, the alignment must be on a 64-word boundary because the required table size is 37 words, and the next power of two is 64, see

Vector table offset register on page 197 .

Arm recommends that the user locates the vector table in either the CODE, SRAM, External

RAM, or External Device areas of the system memory map, see

Cortex ® -M7 configurations on page 30

. Using the Peripheral, Private peripheral bus, or Vendor-specific memory areas

PM0253 Rev 5