PM0253 The Cortex-M7 instruction set
ROR # n
RRX
-
Rotate right n
bits, 1 ≤ n
31.
Rotate right one bit, with extend.
If omitted, no shift occurs, equivalent to
LSL #0
.
If the shift is omitted or
LSL #0
specified, the instruction uses the value in
Rm
.
If the shift is specified, it is applied to the value in
Rm
, and the resulting 32-bit value is used by the instruction. However, the contents in the register
Rm
remain unchanged. Specifying a register with shift also updates the carry flag when used with certain instructions. For
information on the shift operations and how they affect the carry flag, see Shift operations
.
Register shift operations move the bits in a register left or right by a specified number of bits, the shift length . Register shift can be performed:
• Directly by the instructions ASR, LSR, LSL, ROR, and RRX, and the result is written to a destination register.
• During the calculation of Operand2 by the instructions that specify the second operand
as a register with shift, see Flexible second operand on page 64 . The result is used by
the instruction.
The permitted shift lengths depend on the shift type and the instruction, see the individual instruction description or
Flexible second operand on page 64 . If the shift length is 0, no shift
occurs. Register shift operations update the carry flag except when the specified shift length is 0. The following sub-sections describe the various shift operations and how they affect the carry flag. In these descriptions, Rm is the register containing the value to be shifted, and n is the shift length.
ASR
Arithmetic shift right by n bits moves the left-hand 32n bits of the register Rm , to the right by n places, into the right-hand 32n bits of the result. And it copies the original bit[31] of the register into the left-hand n
bits of the result. See Figure 12 on page 66
.
The ASR # n operation can be used to divide the value in the register Rm by 2 n
, with the result being rounded towards negative-infinity.
When the instruction is ASRS or when ASR # n is used in Operand2 with the instructions
MOVS, MVNS, ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to the last bit shifted out, bit[ n -1], of the register Rm .
• If n is 32 or more, then all the bits in the result are set to the value of bit[31] of Rm .
• If n is 32 or more and the carry flag is updated, it is updated to the value of bit[31] of
Rm .
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The Cortex-M7 instruction set
Figure 12. ASR
PM0253
5 4 3 2 1 0
Carry
Flag
31
MSv39652V1
LSR
Logical shift right by n bits moves the left-hand 32n bits of the register Rm , to the right by n places, into the right-hand 32n bits of the result. And it sets the left-hand n bits of the result
to 0. See Figure 13
.
The LSR # n operation can be used to divide the value in the register Rm by 2 n , if the value is regarded as an unsigned integer.
When the instruction is LSRS or when LSR # n is used in Operand2 with the instructions
MOVS, MVNS, ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to the last bit shifted out, bit[ n -1], of the register Rm .
• If n is 32 or more, then all the bits in the result are cleared to 0.
• If n is 33 or more and the carry flag is updated, it is updated to 0.
Figure 13. LSR
0 0 0
Carry
Flag
31 5 4 3 2 1 0
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MSv39679V1
LSL
Logical shift left by n bits moves the right-hand 32n bits of the register Rm , to the left by n places, into the left-hand 32n bits of the result. And it sets the right-hand n bits of the result
to 0. See Figure 14 on page 67 .
The user can use the LSL # n operation to multiply the value in the register Rm by 2 n
, if the value is regarded as an unsigned integer or a two’s complement signed integer. Overflow can occur without warning.
When the instruction is LSLS or when LSL # n , with non-zero n , is used in Operand2 with the instructions MOVS, MVNS, ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to the last bit shifted out, bit[32n ], of the register Rm . These instructions do not affect the carry flag when used with LSL #0.
• If n is 32 or more, then all the bits in the result are cleared to 0.
• If n is 33 or more and the carry flag is updated, it is updated to 0.
PM0253 Rev 5
PM0253 The Cortex-M7 instruction set
Figure 14. LSL
0 0 0
31 5 4 3 2 1 0
Carry
Flag
MSv39678V1
ROR
Rotate right by n bits moves the left-hand 32n bits of the register Rm , to the right by n places, into the right-hand 32n bits of the result. And it moves the right-hand n bits of the register into the left-hand n
bits of the result. See Figure 15 .
When the instruction is RORS or when ROR # n is used in Operand2 with the instructions
MOVS, MVNS, ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to the last bit rotation, bit[ n -1], of the register Rm .
• If n is 32, then the value of the result is same as the value in Rm , and if the carry flag is updated, it is updated to bit[31] of Rm .
• ROR with shift length, n , more than 32 is the same as ROR with shift length n -32.
Figure 15. ROR
Carry
Flag
31 5 4 3 2 1 0
MSv39685V1
RRX
Rotate right with extend moves the bits of the register Rm to the right by one bit. And it
copies the carry flag into bit[31] of the result. See Figure 16 on page 67 .
When the instruction is RRXS or when RRX is used in Operand2 with the instructions
MOVS, MVNS, ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to bit[0] of the register Rm .
Figure 16. RRX
Carry
Flag
31 30 1 0
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MSv39686V1
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