Cache type register. STMicroelectronics STM32H7S3L8, STM32H7R3L8, STM32H7S7A8, STM32H7R3V8, STM32H7R3R8, STM32H7S3Z8, STM32H7S3I8, STM32H7S3V8, STM32H7S7Z8, STM32H7R7I8

Cortex-M7 peripherals

Table 78. CLIDR bit assignments (continued)

Bits Name Function

[14:12] CL 5

[11:9] CL 4

[8:6]

[5:3]

[2]

CL 3

CL 2

CL 1

[1]

[0]

CL 1

CL 1

0b000 : No cache at CL 5.

0b000 : No cache at CL 4.

0b000 : No cache at CL 3.

0b000 : No cache at CL 2.

RAZ: Indicates no unified cache at CL1.

1: Data cache is implemented.

0: No data cache is implemented.

1: An instruction cache is implemented.

0: No instruction cache is implemented.

PM0253

The CTR provides information about the cache architecture. See the register summary in

Table 77 on page 217

for its attributes. The bit assignments are:

31 29 28 27 24 23

Figure 45. CTR bit assignments

20 19 16 15 14 13 4 3 0

1 0 0 0 CWG ERG DMinLine 1 1 0 0 0 0 0 0 0 0 0 0 IminLine

Format

MSv39663V1

Bits Name

Table 79. CTR bit assignments

Description

[31:29] Format

[28] -

[27:24] CWG

Register format.

0b100 : Armv7 register format.

Reserved, RAZ.

Cache Writeback Granule.

0b0011 : 8 word granularity for the Cortex

®

-M7 processor.

[23:20] ERG

[19:16] DMinLine

[15:14] -

Exclusives Reservation Granule.

0b0000 : The local monitor within the processor does not hold any physical address. It treats any STREX instruction access as matching the address of the previous LDREX instruction. This means that the implemented exclusive reservation granule is the entire memory address range.

Smallest cache line of all the data and unified caches under the core control.

0b0011: 8 words for the Cortex

®

-M7 processor.

All bits RAO.

218/254 PM0253 Rev 5