Address alignment. STMicroelectronics STM32H7S3L8, STM32H7R3L8, STM32H7S7A8, STM32H7R3V8, STM32H7R3R8, STM32H7S3Z8, STM32H7S3I8, STM32H7S3V8, STM32H7S7Z8, STM32H7R7I8

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The Cortex-M7 instruction set PM0253

An aligned access is an operation where a word-aligned address is used for a word, dual word, or multiple word access, or where a halfword-aligned address is used for a halfword access. Byte accesses are always aligned.

The Cortex

-M7 processor supports unaligned access only for the following instructions:

• LDR, LDRT.

• LDRH, LDRHT.

• LDRSH, LDRSHT.

• STR, STRT.

• STRH, STRHT.

All other load and store instructions generate a UsageFault exception if they perform an unaligned access, and therefore their accesses must be address aligned. For more information about UsageFaults see

Fault handling on page 47 .

Unaligned accesses are usually slower than aligned accesses. In addition, some memory regions might not support unaligned accesses. Therefore, Arm recommends that programmers ensure that accesses are aligned. To trap accidental generation of unaligned accesses, use the UNALIGN_TRP bit in the Configuration and Control register, see

Configuration and control register on page 200

A PC-relative expression or label is a symbol that represents the address of an instruction or literal data. It is represented in the instruction as the PC value plus or minus a numeric offset. The assembler calculates the required offset from the label and the address of the current instruction. If the offset is too big, the assembler produces an error.

• For B, BL, CBNZ, and CBZ instructions, the value of the PC is the address of the current instruction plus 4 bytes.

• For all other instructions that use labels, the value of the PC is the address of the current instruction plus 4 bytes, with bit[1] of the result cleared to 0 to make it wordaligned.

• The assembler might permit other syntaxes for PC-relative expressions, such as a label plus or minus a number, or an expression of the form [PC, #number].

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Most data processing instructions can optionally update the condition flags in the

Application Program Status register (APSR) according to the result of the operation, see

Application program status register on page 23 . Some instructions update all flags, and

some only update a subset. If a flag is not updated, the original value is preserved. See the instruction descriptions for the flags they affect.

The user can execute an instruction conditionally, based on the condition flags set in another instruction, either:

• Immediately after the instruction that updated the flags.

• After any number of intervening instructions that have not updated the flags.

Conditional execution is available by using conditional branches or by adding condition code

suffixes to instructions. See Table 26 on page 70 for a list of the suffixes to add to

PM0253 Rev 5

PM0253 The Cortex-M7 instruction set instructions to make them conditional instructions. The condition code suffix enables the processor to test a condition based on the flags. If the condition test of a conditional instruction fails, the instruction:

• Does not execute.

• Does not write any value to its destination register.

• Does not affect any of the flags.

• Does not generate any exception.

Conditional instructions, except for conditional branches, must be inside an If-Then instruction block. See

IT on page 148

for more information and restrictions when using the

IT instruction. Depending on the vendor, the assembler might automatically insert an IT instruction if there are conditional instructions outside the IT block.

Use the CBZ and CBNZ instructions to compare the value of a register against zero and branch on the result.

This section describes:

•

The condition flags on page 69 .

•

Condition code suffixes on page 70

The condition flags

The APSR contains the following condition flags:

N Set to 1 when the result of the operation was negative, cleared to 0 otherwise.

Set to 1 when the result of the operation was zero, cleared to 0 otherwise.

Set to 1 when the operation resulted in a carry, cleared to 0 otherwise.

Set to 1 when the operation caused overflow, cleared to 0 otherwise.

For more information about the APSR see

Program status register on page 22

The C condition flag is set in one of four ways:

• For an addition, including the comparison instruction CMN, C is set to 1 if the addition produced a carry (that is, an unsigned overflow), and to 0 otherwise.

• For a subtraction, including the comparison instruction CMP, C is set to 0 if the subtraction produced a borrow (that is, an unsigned underflow), and to 1 otherwise.

• For non-addition or subtractions that incorporate a shift operation, C is set to the last bit shifted out of the value by the shifter.

• For other non-addition or subtractions, C is normally left unchanged. See the individual instruction descriptions for any special cases.

Overflow occurs when the sign of the result, in bit[31], does not match the sign of the result had the operation been performed at infinite precision, for example:

• If adding two negative values results in a positive value.

• If adding two positive values results in a negative value.

• If subtracting a positive value from a negative value generates a positive value.

• If subtracting a negative value from a positive value generates a negative value.

The Compare operations are identical to subtracting, for CMP, or adding, for CMN, except that the result is discarded. See the instruction descriptions for more information.

Most instructions update the status flags only if the S suffix is specified. See the instruction descriptions for more information.

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The Cortex-M7 instruction set PM0253

Condition code suffixes

The instructions that can be conditional have an optional condition code, shown in syntax descriptions as { cond }. Conditional execution requires a preceding IT instruction. An instruction with a condition code is only executed if the condition code flags in the APSR

meet the specified condition. Table 26

shows the condition codes to use.

The conditional execution can be used with the IT instruction to reduce the number of branch instructions in the code.

Table 26 also shows the relationship between condition code suffixes and the N, Z, C, and V

flags.

Suffix Flags

Table 26. Condition code suffixes

Meaning