The Cortex-M7 instruction set PM0253
Restrictions
In these instructions:
• Operand2 must not be SP and must not be PC
• Rd can be SP only in ADD and SUB, and only with the additional restrictions:
– Rn must also be SP.
– Any shift in Operand2 must be limited to a maximum of 3 bits using LSL.
• Rn can be SP only in ADD and SUB
• Rd can be PC only in the ADD{ cond } PC, PC, Rm instruction where:
– The S suffix must not be specified.
– Rm must not be PC and must not be SP.
– If the instruction is conditional, it must be the last instruction in the IT block.
• With the exception of the ADD{ cond } PC, PC, Rm instruction, Rn can be PC only in
ADD and SUB, and only with the additional restrictions:
– The S suffix must not be specified.
– The second operand must be a constant in the range 0 to 4095.
– When using the PC for an addition or a subtraction, bits[1:0] of the PC are rounded to 0b00 before performing the calculation, making the base address for the calculation word-aligned.
– If the user wants to generate the address of an instruction, the constant has to be adjusted based on the value of the PC. Arm recommends using the ADR instruction instead of ADD or SUB with Rn equal to the PC, because the assembler automatically calculates the correct constant for the ADR instruction.
When Rd is PC in the ADD{ cond } PC, PC, Rm instruction:
• Bit[0] of the value written to the PC is ignored.
• A branch occurs to the address created by forcing bit[0] of that value to 0.
Condition flags
If
S
is specified, these instructions update the N, Z, C and V flags according to the result.
Examples
ADD R2, R1, R3
SUBS R8, R6, #240 ; Sets the flags on the result.
RSB R4, R4, #1280 ; Subtracts contents of R4 from 1280.
ADCHI R11, R0, R3 ; Only executed if C flag set and Z.
; flag clear.
Multiword arithmetic examples
Example 3-4: 64-bit addition shows two instructions that add a 64-bit integer contained in R2
and R3 to another 64-bit integer contained in R0 and R1, and place the result in R4 and R5.
Example 3-4: 64-bit addition
ADDS R4, R0, R2 ; Add the least significant words.
ADC R5, R1, R3 ; Add the most significant words with carry
.
The multiword values do not have to use consecutive registers. Example 3-5: 96-bit
88/254 PM0253 Rev 5
