Memory access instructions. STMicroelectronics STM32H7S3L8, STM32H7R3L8, STM32H7S7A8, STM32H7R3V8, STM32H7R3R8, STM32H7S3Z8, STM32H7S3I8, STM32H7S3V8, STM32H7S7Z8, STM32H7R7I8

The Cortex-M7 instruction set

3.4 Memory access instructions

Table 27 shows the memory access instructions:

PM0253

Mnemonic

Table 27. Memory access instructions

Brief description See

ADR Generate PC-relative address

CLREX Clear Exclusive

LDM{mode} Load Multiple registers

ADR on page 73

CLREX on page 84

LDM and STM on page 79

LDR{type}

LDR{type}

Load register using immediate offset

Load register using register offset

LDR and STR, immediate offset on page 73

LDR and STR, register offset on page 76

LDR{type}T Load register with unprivileged access

LDR and STR, unprivileged on page 77

LDR Load register using PC-relative address

LDR, PC-relative on page 78

LDRD Load register Dual

LDR and STR, immediate offset on page 73

LDREX{type} Load register Exclusive

PLD Preload Data.

POP Pop registers from stack

LDREX and STREX on page 83

PLD on page 81

PUSH and POP on page 82

PUSH Push registers onto stack

STM{mode} Store Multiple registers

STR{type} Store register using immediate offset

PUSH and POP on page 82

LDM and STM on page 79

LDR and STR, immediate offset on page 73

STR{type} Store register using register offset

LDR and STR, register offset on page 76

STR{type}T Store register with unprivileged access

LDR and STR, unprivileged on page 77

STREX{type} Store register Exclusive

LDREX and STREX on page 83

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