Exception model. STMicroelectronics STM32H7S3L8, STM32H7R3L8, STM32H7S7A8, STM32H7R3V8, STM32H7R3R8, STM32H7S3Z8, STM32H7S3I8, STM32H7S3V8, STM32H7S7Z8, STM32H7R7I8

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PM0253 The Cortex-M7 processor

For example: uint16_t value; uint16_t *address = 0x20001002; value = __LDREXH (address); // load 16-bit value from memory address

0x20001002

This section describes the exception model. It describes:

•

Exception states .

•

Exception types .

•

Exception handlers on page 41 .

•

Vector table on page 42

•

Exception priorities on page 43 .

•

Interrupt priority grouping on page 43

•

Exception entry and return on page 44 .

Each exception is in one of the following states:

Inactive

Pending

The exception is not active and not pending.

The exception is waiting to be serviced by the processor.

Active

An interrupt request from a peripheral or from software can change the state of the corresponding interrupt to pending.

An exception that is being serviced by the processor but has not completed.

Note: An exception handler can interrupt the execution of another exception handler. In this case both exceptions are in the active state.

Active and pending The exception is being serviced by the processor and there is a pending exception from the same source.

The exception types are:

Reset Reset is invoked on power up or a warm reset. The exception model treats reset as a special form of exception. When reset is asserted, the operation of the processor stops, potentially at any point in an instruction. When reset is deasserted, execution restarts from the address provided by the reset entry in the vector table. Execution restarts as privileged execution in Thread mode.

PM0253 Rev 5 39/254

The Cortex-M7 processor PM0253

-14

3 -13

4 -12

7-10

12-13

NMI

HardFault

SVCall

PendSV

SysTick

Interrupt (IRQ)

A NonMaskable Interrupt (NMI) can be signalled by a peripheral or triggered by software. This is the highest priority exception other than reset. It is permanently enabled and has a fixed priority of -2. NMIs cannot be:

• Masked or prevented from activation by any other exception.

• Preempted by any exception other than Reset.

A HardFault is an exception that occurs because of an error during normal or exception processing. HardFaults have a fixed priority of -1, meaning they have higher priority than any exception with configurable priority.

A Supervisor Call (SVC) is an exception that is triggered by the SVC instruction. In an OS environment, applications can use SVC instructions to access OS kernel functions and device drivers.

PendSV is an interrupt-driven request for system-level service. In an

OS environment, use PendSV for context switching when no other exception is active.

A SysTick exception is an exception the system timer generates when it reaches zero. Software can also generate a SysTick exception. In an OS environment, the processor can use this exception as system tick.

An interrupt, or IRQ, is an exception signalled by a peripheral, or generated by a software request. All interrupts are asynchronous to instruction execution. In the system, peripherals use interrupts to communicate with the processor.

Table 19. Properties of the different exception types

Exception number

(1)

IRQ number

(1)

Exception type

Priority

Vector address

(2)

Activation

-11

-5