Nested Vectored Interrupt Controller. STMicroelectronics STM32H7S3L8, STM32H7R3L8, STM32H7S7A8, STM32H7R3V8, STM32H7R3R8, STM32H7S3Z8, STM32H7S3I8, STM32H7S3V8, STM32H7S7Z8, STM32H7R7I8

Cortex-M7 peripherals PM0253

4.2 Nested Vectored Interrupt Controller

This section describes the NVIC and the registers it uses. The NVIC supports:

• 1 to 240 interrupts.

• A programmable priority level of 0-255 for each interrupt. A higher level corresponds to a lower priority, so level 0 is the highest interrupt priority.

• Level and pulse detection of interrupt signals.

• Dynamic reprioritization of interrupts.

• Grouping of priority values into group priority and subpriority fields.

• Interrupt tail-chaining.

• An external Non Maskable Interrupt (NMI)

The processor automatically stacks its state on exception entry and unstacks this state on exception exit, with no instruction overhead. This provides low latency exception handling.

The hardware implementation of the NVIC registers is:

Address Name

0xE000E100-

0xE000E11C

0XE000E180-

0xE000E19C

0XE000E200-

0xE000E21C

0XE000E280-

0xE000E29C

0xE000E300-

0xE000E31C

0xE000E400-

0xE000E4EF

NVIC_ISER0-

NVIC_ISER7

NVIC_ICER0-

NVIC_ICER7

NVIC_ISPR0-

NVIC_ISPR7

NVIC_ICPR0-

NVIC_ICPR7

NVIC_IABR0-

NVIC_IABR7

NVIC_IPR0-

NVIC_IPR59

Table 40. NVIC register summary

Type

Required privilege

Reset value

RW

RW

RW

RW

RW

Privileged

Privileged

Privileged

Privileged

Privileged

0x00000000

0x00000000

0x00000000

0x00000000

0x00000000

Description

Interrupt set-enable registers on page 185

Interrupt clear-enable registers on page 186

Interrupt set-pending registers on page 186

Interrupt clear-pending registers on page 187

Interrupt active bit registers on page 188

RW Privileged 0x00000000

Interrupt priority registers on page 188

0xE000EF00 STIR WO Configurable

(1)

0x00000000

Software trigger interrupt register on page 189

1. See the register description for more information.

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