PM0253 Cortex-M7 peripherals
The VTOR indicates the offset of the vector table base address from memory address
0x00000000. See the register summary in Table 50 on page 192 for its attributes. The bit
assignments are:
Figure 27. VTOR bit assignments
31 9 8 0
TBLOFF Reserved
MSv39699V1
Bits Name
[31:9] TBLOFF
[8:0] -
Table 54. VTOR bit assignments
Function
Vector table base offset field. It contains bits [29:7] of the offset of the table base from the bottom of the memory map.
Reserved.
When setting TBLOFF, the user must align the offset to the number of exception entries in the vector table.
The table alignment requirements mean that bits [8:0] of the table offset are always zero.
The AIRCR provides priority grouping control for the exception model, endian status for data accesses, and reset control of the system. See the register summary in
Table 50 on page 192
and
Table 55 on page 198
for its attributes.
To write to this register, the user must write 0x5FA to the VECTKEY field, otherwise the processor ignores the write.
The bit assignments are:
Figure 28. AIRCR bit assignments
31 16 15 14 11 10
On read: VECTKEYSTAT
On write: VECTKEY
Reserved
ENDIANNESS PRIGROUP
Reserved for Debug use
8 7
Reserved
3
SYSRESETREQ
VECTCLRACTIVE
VECTRESET
2 1 0
MSv39651V1
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Cortex-M7 peripherals PM0253
[31:16]
[15]
[14:11] -
[10:8]
[7:3]
[2]
[1]
[0]
Bits Name
Read:
VECTKEYSTAT
Write: VECTKEY
ENDIANNESS
PRIGROUP
- -
SYSRESETREQ
VECTCLRACTIVE WO
VECTRESET
Table 55. AIRCR bit assignments
Type Function
-
RW
RO
RW
WO
WO
Register key:
Reads as 0xFA05
On writes, write 0x5FA to VECTKEY, otherwise the write is ignored.
Data endianness bit:
0: Little-endian.
Reserved
Interrupt priority grouping field. This field determines the split of group priority from subpriority, see
Binary point
.
Reserved.
System reset request:
0: No system reset request.
1: Asserts a signal to the outer system that requests a reset.
This is intended to force a large system reset of all major components except for debug.
This bit reads as 0.
Reserved for Debug use. This bit reads as 0. When writing to the register the user must write 0 to this bit, otherwise behavior is Unpredictable.
Reserved for Debug use. This bit reads as 0. When writing to the register the user must write 0 to this bit, otherwise behavior is Unpredictable.
Binary point
The PRIGROUP field indicates the position of the binary point that splits the PRI_ n fields in the Interrupt Priority Registers into separate group priority and subpriority fields.
Table 56
shows how the PRIGROUP value controls this split.
If the user implements fewer than 8 priority bits he might require more explanation here, and want to remove invalid rows from the table, and modify the entries in the number of columns.
Table 56. Priority grouping
Interrupt priority level value, PRI_ N [7:0]
PRIGROUP Binary point
(1)
0b000
0b001
0b010
0b011
0b100 bxxxxxxx.y
bxxxxxx.yy
bxxxxx.yyy
bxxxx.yyyy
bxxx.yyyyy
Number of
Group priority bits
[7:1]
[7:2]
[7:3]
[7:4]
[7:5]
Subpriority
[0]
[1:0]
[2:0]
[3:0]
[4:0] bits
128
64
32
16
8
Group priorities
Subpriorities
2
4
8
16
32
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