Cortex-M7 peripherals PM0253
Bits
[1]
[0]
Name
Table 58. CCR bit assignments (continued)
Type Function
USERSETMPEND RW
NONBASETHRDE
NA
RW
Enables unprivileged software access to the STIR, see
Software trigger interrupt register on page 189
:
0: Disable.
1: Enable.
Indicates how the processor enters Thread mode:
0: Processor can enter Thread mode only when no exception is active.
1: Processor can enter Thread mode from any level under
the control of an EXC_RETURN value, see Exception return on page 46 .
The SHPR1-SHPR3 registers set the priority level, 0 to 255 of the exception handlers that have configurable priority.
SHPR1-SHPR3 are byte accessible. See the register summary in Table 50 on page 192
for their attributes.
The system fault handlers and the priority field and register for each handler are:
Handler
MemManage
BusFault
UsageFault
SVCall
PendSV
SysTick
Table 59. System fault handler priority fields
Field Register description
PRI_4
PRI_5
PRI_6
PRI_11
PRI_14
PRI_15
System handler priority register 1
System handler priority register 2
System handler priority register 3
Each PRI_ n field is 8 bits wide, but the processor implements only bits[7:M] of each field, and bits[M-1:0] read as zero and ignore writes.
System handler priority register 1
The bit assignments are:
Figure 31. SHPR1 bit assignements
31 24 23 16 15 8 7 0
Reserved PRI_6 PRI_5 PRI_4
MSv39689V1
202/254 PM0253 Rev 5
PM0253 Cortex-M7 peripherals
Bits
[31:24]
[23:16]
[15:8]
[7:0]
Name
PRI_7
PRI_6
PRI_5
PRI_4
Table 60. SHPR1 register bit assignments
Function
Reserved
Priority of system handler 6, UsageFault
Priority of system handler 5, BusFault
Priority of system handler 4, MemManage
System handler priority register 2
The bit assignments are:
Figure 32. SHPR2 bit assignments
31 24 23
PRI_11 Reserved
0
MSv39690V1
Bits
[31:24]
[23:0]
Table 61. SHPR2 register bit assignments
Name Function
-
PRI_11 Priority of system handler 11, SVCall
Reserved
System handler priority register 3
The bit assignments are:
Figure 33. SHPR3 bit assignments
31 24 23 16 15
PRI_15 PRI_14 Reserved
0
MSv39691V1
Bits
[31:24]
[23:16]
[15:0]
Table 62. SHPR3 register bit assignments
Name Function
-
PRI_15
PRI_14
Priority of system handler 15, SysTick exception
Priority of system handler 14, PendSV
Reserved
PM0253 Rev 5 203/254
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