Initialization/application information. STMicroelectronics SPC58xNx 32-bit Power Architecture microcontroller, SPC58NN84C3, SPC58NN84E7

Enhanced Direct Memory Access (eDMA) RM0421

23.5 Initialization/application information

The following sections discuss initialization of the eDMA and programming considerations.

23.5.1 eDMA initialization

A typical initialization of the eDMA has the following sequence:

1.

Write the CR register if a configuration other than the default is desired.

2. Write the channel priority levels into the DCHPRI n registers if a configuration other than the default is desired.

3. Enable error interrupts in the EEI registers if so desired.

4. Write the 32-byte TCD for each channel that may request service.

5. Enable any hardware service requests via the ERQ register.

6. Request channel service by software (setting the TCD n _CSR[START] bit) or hardware

(slave device asserting its eDMA peripheral request signal).

After any channel requests service, a channel is selected for execution based on the arbitration and priority levels written into the programmer’s model. The eDMA engine reads

the entire TCD, including the TCD control and status fields (shown in Table 316 ) for the

selected channel into its internal address path module. As the TCD is read, the first transfer is initiated on the internal bus unless a configuration error is detected. Transfers from the source (as defined by the source address, TCD n _SADDR) to the destination (as defined by the destination address, TCD n _DADDR) continue until the specified number of bytes

(TCD n _NBYTES) are transferred. When the transfer is complete, the eDMA engine’s local

TCD n _SADDR, TCD n _DADDR, and TCD n _CITER are written back to the main TCD memory and any minor loop channel linking is performed, if enabled. If the major loop is exhausted, further post processing executes (interrupts, major loop channel linking, and scatter/gather operations) if enabled.

Table 316. TCD control and status fields

TCD n _CSR field name

Description

START

ACTIVE

Control bit to start channel explicitly when using a software initiated DMA service

(automatically cleared by hardware)

Status bit indicating the channel is currently in execution

DONE

D_REQ

Status bit indicating major loop completion (cleared by software when using a software initiated DMA service)

Control bit to disable DMA request at end of major loop completion when using a hardware initiated DMA service

Control bits for throttling bandwidth control of a channel BWC

E_SG Control bit to enable scatter-gather feature

INT_HALF Control bit to enable interrupt when major loop is half complete

INT_MAJ Control bit to enable interrupt when major loop completes

Figure 212 shows how each DMA request initiates one minor-loop transfer (iteration)

without CPU intervention. DMA arbitration can occur after each minor loop, and one level of

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minor loop DMA preemption is allowed. The number of minor loops in a major loop is specified by the beginning iteration count (BITER).

Figure 212. Example of multiple loop iterations

#URRENTMAJOR

LOOPITERATION

COUNT#)4%2

-INORLOOP

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-INORLOOP -AJORLOOP

$-!REQUEST

-INORLOOP

Figure 213 lists the memory array terms and how the TCD settings interrelate.

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