Embedded Flash Memory
33 Embedded Flash Memory
RM0421
33.1 Introduction
The Flash Memory module serves as electrically programmable and erasable nonvolatile memory, for instructions and data storage.
The Flash Memory module is a nonvolatile, solid-state silicon memory device consisting of blocks of single transistor storage elements, an electrical means for selectively adding
(programming) and removing (erasing) charge from these elements, and a means of selectively sensing (reading) the charge stored in these elements.
The Flash Memory module has two functional units:
• The Flash core: it is composed of a common high voltage HV block and a Flash array which can contain one or more Flash partitions. Each Flash partition is composed of arrayed nonvolatile storage elements, sense amplifiers, row decoders and column decoders. The arrayed storage elements in the Flash partitions are subdivided into physically separate units referred to as blocks.
• The Memory interface: it contains the registers and logic which control the operation of the Flash core and contains two main ports: the Array Interface and the Registers
Interface. The memory interface is also the interface between the Flash Memory module and a Bus Interface Unit (BIU) and contains the ECC and redundancy logic.
33.1.1 Overview
The 6608 KB Flash Memory module contains six array partitions. Read-While-Write operations are only possible for separate partitions, meaning fetching/reading from one (or more) partition(s) while a program/erase operation is active on another partition. Each module counts as an RWW partition.
EEPROM emulation is managed as 4 × 64 KB blocks in two partitions, referred to as Data
Flash.
HSM EEPROM emulation is managed as 2 × 16 KB blocks in two partition, referred to as
HSM Data Flash.
The Modify operations are managed by an embedded Flash Program/Erase Controller
(FPEC). Commands to the FPEC are delivered through a User Registers interface.
The Read Data bus is 256-wide, while the Flash registers are on a separate, 32-bit bus.
The high voltages needed for Program and Erase operations are internally generated and are common for the six partitions.
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Figure 345. Flash memory module structure
Flash core
Flash memory module
Flash array RWR0:
5 RWW partitions
Code Flash
2128 KB
Partition 0
Code Flash
2144 KB
Partition 1
— — — — — — — — — — —
Data Flash
128 KB
Partition 2
Data Flash
128 KB
Partition 3
— — — — — — — — — — —
Data Flash
32 KB
Partition 4
— — — — — —
Code Flash
2048 KB
Partition 5
— — — — —
Flash array RWR1:
1 RWW partition(s)
HV generator
Array interface
Array interface
Registers interface
Flash
Program/Erase
Controller
Flash registers
Memory interface
Flash
Controller
Flash
Controller
IPS bus
The Flash Memory module is designed for use in embedded applications which require high density non-volatile memories with high-speed Read access.
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The Flash array is addressable:
• For programs in data partition: by word (32 bits) or doubleword (64 bits). ECC granularity is 64 bits.
• For programs in code partition: by word (32 bits) or doubleword (64 bits). ECC granularity is 128 bits.
• For reading code partitions – by page (256 bits).
• For reading data partitions – by half-page (128 bits).
Multiple-word or doubleword writes to the Flash memory may be performed to fill the program page buffer (256 bits), enabling page programming (256 bits – requiring 4 doubleword writes) and quad-page programming (1024 bits – requiring 16 doubleword writes). Code Flash memory reads always return 256, although Read buffering may be performed by the Bus Interface Unit (BIU). The address for each word retrieved within a page differs from the other addresses in the page by address bits (4:2).
Data Flash memory reads always return 128 bits, or two consecutive doublewords of information. The address for each word retrieved within a doubleword differs from the other addresses by address bits (3:2).
The Flash Memory module supports fault tolerance through Error Correction Code (ECC) and error detection. The ECC implemented within the Flash Memory module corrects double bit failures and detects triple bit failures.
The Flash Memory module uses an embedded hardware algorithm implemented in the
Flash Program/Erase Controller to program and erase the Flash partitions.
Control logic that works with the software block-enables and software lock mechanisms are included in the embedded hardware algorithm to guard against accidental program/erase.
The hardware algorithm performs the necessary steps to ensure that the storage elements are programmed and erased with sufficient margin to guarantee data integrity and reliability.
A programmed bit in the Flash array reads as logic level ‘0’ (or low). An erased bit in the
Flash array reads as logic level ‘1’ (or high).
Programming and Erasing of the Flash array requires multiple system clock cycles to complete.
The Program and Erase sequences may be suspended or aborted.
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