e200z4256 Core Debug Support RM0421
Note: recorded in DBSR regardless of the setting of MSR
DE
. The normal DAC1 status bit in the
DBSR is used for recording these events. The IAC status bit is not set if the corresponding
Instruction Address Compare register is linked.
Linking is enabled using control bits in DBCR2 and DBCR8. Note that linking is only available in EDM or IDM. Attempts to use linking otherwise are ignored.
Linked DAC events will not be recorded if a load multiple word or store multiple word type instruction is interrupted prior to completion by a critical input or external input interrupt.
66.2.4 Trap debug event
A Trap debug event (TRAP) occurs if Trap debug events are enabled (DBCR0
TRAP
=1), a
Trap instruction ( tw ) is executed, and the conditions specified by the instruction for the trap are met. This event can occur and be recorded in DBSR regardless of the setting of MSR
DE
When a Trap debug event occurs, the DBSR
TRAP exception.
bit is set to 1 to record the debug
.
66.2.5 Branch Taken debug event
A Branch Taken debug event (BRT) occurs if Branch Taken debug events are enabled
(DBCR0
BRT
=1) and execution is attempted of a branch instruction that will be taken (either an unconditional branch, or a conditional branch whose branch condition is true), and
MSR
DE
=1. Branch Taken debug events are not recognized if MSR
DE execution of the branch instruction and thus DBSR
IDE
=0 at the time of
cannot be set by a Branch Taken debug event. When a Branch Taken debug event is recognized, the DBSR
BRT
bit is set to 1 to record the debug exception, and the address of the branch instruction will be recorded in
DSRR0.
66.2.6 Instruction Complete debug event
An Instruction Complete debug event (ICMP) occurs if Instruction Complete debug events are enabled (DBCR0
ICMP
=1), execution of any instruction is completed, and MSR
DE
=1. If execution of an instruction is suppressed due to the instruction causing some other exception that is enabled to generate an interrupt, then the attempted execution of that instruction does not cause an Instruction Complete debug event. The se_sc instruction does not fall into the category of an instruction whose execution is suppressed, since the instruction actually executes and then generates a System Call interrupt. In this case, the
Instruction Complete debug exception will also be set. When an Instruction Complete debug event is recognized, DBSR
ICMP
is set to 1 to record the debug exception and the address of the next instruction to be executed will be recorded in DSRR0.
Instruction Complete debug events are not recognized if MSR
DE of the instruction, thus DBSR
IDE
=0 at the time of execution
is not generally set by an ICMP debug event.
One circumstance may cause the DBSR
ICMP
and DBSR
IDE
bits to be set. This occurs when an EFPU Round exception occurs. Since the instruction is by definition completed (SRR0 points to the following instruction), this interrupt takes higher priority than the Debug interrupt so as not to be lost, and DBSR
IDE
is set to indicate the imprecise recognition of a
Debug interrupt. In this case, the Debug interrupt will be taken with SRR0 pointing to the instruction following the instruction that generated the EFPU Round exception, and DSRR0 will point to the Round exception handler. In addition to occurring when DBCR0
IDM circumstance can also occur when EDBCR0
EDM which case EDBSR0
IDE
will be set.
=1, this
=1 and the event is hardware-owned, in
3128/4101
RM0421 Rev 5
