Command queue (CMDQ). STMicroelectronics SPC58xNx 32-bit Power Architecture microcontroller, SPC58NN84C3, SPC58NN84E7

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SARADC Queued digital interface (ADCQ) RM0421

Command FIFO (CMDQ) to accept measurement sequence commands from the system.

2. ADC result FIFO (DATAQ) to store and send measurement sequence data to the system.

3. An optional auxiliary data queue (AUXDQ) to interface directly with the other data processing units.

4. DMA interface for the CMDQ.

5. DMA interface for the DATAQ.

6. Per queue control and status registers (Q_REGS).

7. Per queue counters: command counter, sequence counter and sequence ADC command counter.

8. Per queue measurement interval timer ( Δ T) to space measurement commands in a sequence.

9. Optional 8 trigger outputs per queue. The trigger characteristics are controlled by the

SW.

10. Global control and status registers to manage all the queues in one ADCQ.

The following sections describe each entity of the queue in detail.

39.3.1 Command queue (CMDQ)

39.3.1.1 Overview

Every queue module is equipped with a command queue to accept the prepared measurement sequences from the system over the DMA interface. The order of execution of the commands is same as the order of reception.

The command queue is a 32-bit wide FIFO of fixed depth. The depth of each command queue is selected during design configuration. SW can check the depth of each command

queue, CMDQ, by reading 39.4.11: Global Queue Configuration register

(GLBL_Qn_CONFIG)

Figure 504 illustrates the CMDQ structure. The command queue watermark (CMDQ_WM)

defines when the CMDQ DMA/Interrupt request is asserted. When the number of free entries in CMDQ is greater than or equal to the command queue watermark then CMDQ will assert its DMA/Interrupt request. If DMA mode is enabled (CMDQ_DMA_MODE_EN=1) then a DMA request is asserted. The system CPU or DMA controller will push the commands into the CMDQ through the Qn_CMDQ_PUSH register. After every push the

CMDQ_WR_PTR points to the next free entry in the queue. On reaching the top of queue the write pointer wraps around. After every read the CMDQ_RD_PTR points to the next valid entry in the queue.

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When CMDQ is full (CMDQ_FULL=1) and another entry is being pushed then the new entry does not overwrite any entry in the CMDQ and the CMDQ overflow flag

(CMDQ_OVRN_ERR) is set.

39.3.1.2 Command queue errors and error handling

A command queue overrun occurs when the command queue is full and a new data is being written into the command queue. On overrun condition the new command does not overwrite any existing command. Only a command queue overrun flag is set and if error reporting is enabled then an error interrupt is raised.

A command sequence missing error occurs, when a trigger arrives and the command queue is empty. Command sequence missing error flag is set and if error reporting is enabled then an error interrupt is raised. In this scenario the pending trigger is also registered in the status register. If the sequence starts arriving then it is executed immediately for the pending trigger and the corresponding first data in the data sequence is marked with command missing flag.

39.3.1.3 Command Queue (CMDQ) descriptor

Each command entry of the command queue identifies the type of command, controls the behaviour of the command and has markers to delimit the commands.

The command queue supports three types of commands:

ADC conversion commands.

2. Optional trigger output commands.

3. Dummy commands to insert SW defined spacing between two ADC conversions or to generate SW defined trigger output pulse widths.

The following behaviours are controlled by the control bits in each command:

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Whether to pass the command to ADC or not (dummy command).

2. Whether to bypass the measurement interval timer.

3. Whether to capture the ADC data timestamp for this command.

4. How to align the ADC result data in the data queues, right or left.

5. Which data queue should the result be routed to, DATAQ or AUXDQ or to both.

6. Which ADC CFG to use for the command (sampling times and other parameters).

7. Whether Pre-charge phase is enabled for the channel or not.

8. Whether to raise an interrupt on end of a measurement sequence.

The following data markers delimit the measurement sequence:

Last command marker identifies the end of measurement sequence.

2. Last ADC data marker identifies the last ADC conversion command in a measurement sequence.

Figure 505 and Table 632

capture the bit positions and definitions of the CMDQ descriptor.

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0 1 2 3 4 5

Figure 505. CMDQ descriptor bit fields

6 7 8 9 10 11 12 13 14 15 16:23 24:31

Field

LAST_CMD_OF_SEQ

TS_CAPTURE_EN

ALIGN_DATA_LEFT

BYPASS_TIMER

DUMMY_CMD

ADC_VREF_SEL

Table 632. CMDQ descriptor bit field descriptions

Description

LAST_ADC_CMD

Denotes the last command in a sequence. Last command can also be a dummy command. The measurement sequence stops after this command and waits for a new trigger to start the next sequence in the

CMDQ.

For single conversion set the LAST_CMD and the LAST_ADC_CMD bits in the first command of the sequence.

Denotes that this command in the sequence is the last ADC command.

Since a sequence can end with a dummy command and a dummy command is generally not stored in the data queues, there is no way to mark the last data in the data queues when the sequence ends with a dummy command. This bit allows marking the last ADC data in the

DATAQ and the AUXDQ. This bit has no impact on the measurement sequence processing.

Timestamp capture enable bit. When set timestamp is captured for this command. Usually not all CMD's need a TS capture. First command, last command and suspended commands in a sequence are the main targets for timestamp capture. User can set this bit for first, last or any intermediate commands to enable timestamp capture for that command.

This bit enables capture of timestamp in both the DATAQ and the

AUXDQ.

The queue specific control bits enable/disable the capture of timestamps in the DATAQ and the AUXDQ.

ADC result data stored in data queues is by default aligned right. If

ALIGN_DATA_LEFT bit is set in the command then the ADC data is aligned left in the data queues. This is true only when the result data width is less than 16-bits

When set then the command is executed immediately without waiting for

Δ T to elapse. This bit affects all commands (ADC, dummy and trigger output commands).

When set, it denotes that the command is a dummy command which is not passed to the ADC.

Reserved

To select one of the 2 ADC references for this CMD. Unused for dummy commands.

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Table 632. CMDQ descriptor bit field descriptions (continued)

Field Description

ADC_PRECHG_EN

12:13

ADC_CFG_SEL[30:31]

DATA_TO_AUXDQ

DATA_TO_DATAQ

16:23

TRIG_OUT[24:31]

24:31

ADC_CH_NUM[24:31]

When set then PRECHG phase is enabled for the channel. Unused for dummy commands.

To select one of the 4 ADC parameters for this command. These bits should also be defined for dummy commands so that the correct Δ C can be applied to the dummy commands.

Is defined only when AUXDQ is present in the queue. When set the

ADC result is routed to AUX DATAQ.

ADC Data routing bit. Is defined only when AUXDQ is present in the queue. When AUXDQ is not present then by default ADC data is routed to DATAQ only. When set the ADC result is routed to DATAQ.

One hot digital trigger outputs. One hot encoding allows driving them simultaneously from a single command.

SW has to manage the allocation of trigger outputs between queues using the TRIG_OUT_UNMASK [7:0] bits of the Q_TRGO_SETUP register.

Trigger output pulse width is defined by SW in multiples of

BYPASS_TIMER is set then Δ T is skipped.

Δ T. When

Channel Number of ADC for the current command. All values from 0 to

255 are valid. Use a dummy command to stop forwarding the command to ADC, in which case this field is unused.

Figure 506 captures few valid combinations of a command queue descriptor with data

routed to both data queues.

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