Queue counters. STMicroelectronics SPC58xNx 32-bit Power Architecture microcontroller, SPC58NN84C3, SPC58NN84E7
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SARADC Queued digital interface (ADCQ)
Figure 518. Trigger output timing
RM0421
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39.3.6 Queue counters
Queue counters keep track of the number of commands, the number of sequences and the number of ADC commands in a sequence. This can be used by the SW to synchronize conversions across queues in multiple ADCQs.
39.3.6.1 Command Counter (CMD_CNTR)
Each queue, normal and injected, provides a command counter (CMD_CNTR) to track the f total number of commands executed, including dummy commands. The main purpose is to use counters on different queue modules as an indicator of synchronous run. The counter increments every time an ADC result is stored in the DATAQ or on completion of a dummy command. This 16-bit counter wraps around once it reaches its maximum value. Counter wrap-around is registered in the queue status register and can signal it through an interrupt.
The SW can read the current value at any time. This counter is cleared in any of the following cases:
RM0421 Rev 5
RM0421 SARADC Queued digital interface (ADCQ)
1.
When the SW issues a reset queue counters command through the queue control register.
2. When the SW issues a global reset queue counters command and the queue is participating in this global command.
3. When the SW issues a queue abort command.
4. When the SW issues a global abort command and the queue is participating in global abort operation.
39.3.6.2 Sequence Counter (SEQ_CNTR)
Each queue, normal and injected, provides a sequence counter (SEQ_CNTR) to track the number of sequences executed. The counter increments on completion of a command sequence. This 16-bit counter wraps around once it reaches its maximum value. Counter wrap-around is registered in the queue status register and can signal this through an interrupt. The SW can read the current value at any time. This counter is cleared in any of the following cases:
1.
When the SW issues a reset queue counters command through the queue control register.
2. When the SW issues a global reset queue counters command and the queue is participating in this global command.
3. When the SW issues a queue abort command.
4. When the SW issues a global abort command and the queue is participating in a global abort operation.
39.3.6.3 Sequence ADC Command Counter (SEQ_ADC_CNTR)
Each queue, normal and injected, provides a sequence ADC counter (SEQ_ADC_CNTR) which keeps track of total number of ADC commands executed in a sequence. The counter increments on completion of each ADC command in a sequence. This 8-bit counter resets at start of next sequence.
If there are more than 256 ADC commands in a sequence this counter wraps around. The counter wrap-around is registered in the queue status register and can signal this through an interrupt.
For each queue it is possible to enable the attachment of this count in the sequence status word inside the DATAQ. The sequence status word is always at the end of the sequence in a DATAQ.
The SW can read the current value at any time. This counter is cleared in any of the following cases:
1.
Automatically when a sequence ends.
2. When the SW issues a reset queue counters command through the queue control register.
3. When the SW issues a global reset queue counters command and the queue is participating in this global command.
4. When the SW issues a queue abort command.
5. When the SW issues a global abort command and the queue is participating in a global abort operation.
RM0421 Rev 5
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