SARADC Queued digital interface (ADCQ) RM0421
When an injected sequence suspends a command in a normal queue that is waiting for its
Δ T to elapse then the Δ T is restarted from its reload value when the suspended sequence resumes.
39.3.4 Queue trigger input system
Each queue can support up to 32 hardware trigger inputs. The number of hardware triggers is defined during design configuration. The SW can check the number of HW trigger inputs
that are present in the design by reading 39.4.10: Global module Configuration register
(GLBL_CONFIG) .
All hardware trigger inputs are routed to every queue. And each queue can choose which hardware trigger(s) to use to trigger its command sequence. So hardware trigger inputs are not classified as injected or normal triggers. Triggers enabled in queue-0 become injected triggers and triggers enabled in queues 1,2 and 3 become normal triggers.
39.3.4.1 Trigger enabling
Each queue has edge register which enables the selection of the rising ( Section 39.4.15:
Queue Rise edge Enable register (Qn_RISEN)
) or falling (
Section 39.4.16: Queue Fall edge
Enable register (Qn_FALLEN) ) edge (or both) for each hardware trigger input. When neither
edge is enabled then the corresponding hardware trigger input is ignored.
The final trigger of each queue can be individually enabled or disabled using the queue
control register ( Section 39.4.18: Queue Control register (Qn_CTRL)
).
A trigger can be synchronously enabled or disabled for multiple queues in one ADCQ using
the global control register ( Section 39.4.2: Global Control Register (GLBL_Q_CTRL)
).
Each queue can participate in a synchronous global trigger enable operation across multiple
ADCQs by unmasking its global trigger enable input.
39.3.4.2 SW triggering
The SW can trigger a queue measurement sequence using the queue control register.
The SW can synchronously trigger measurement sequence of multiple queues in one
ADCQ using the global control register.
Each queue can participate in a synchronous global SW trigger operation across multiple
ADCQ by unmasking its global SW trigger input.
39.3.4.3 Multiple HW triggers
Enabling multiple rising or falling register bits will enable multiple hardware inputs to trigger a measurement sequence in a queue.
39.3.4.4 Trigger system illustration
Figure 514 illustrates the trigger input system.
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RM0421 SARADC Queued digital interface (ADCQ)
Figure 514. Queue trigger input system
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