LVDS Fast Asynchronous Serial Transmission – Interprocessor Communications RM0421
51.5 Features
• Supports dual mode (register configurable Master/Slave)
• Supports asynchronous data transfer rates up to the maximum data rated shown in the product Datasheet
• Transmits and receives data, CTS, ICLC and unsolicited frames
• Provision of five interrupts for Tx and Rx channels.
• Supports processor controlled transfer of ICLC frame with 8-bit payload size to implement the data rate changes and test modes
• Supports LFAST defined CTS controlled data transfer. No dependency between data transmission and reception unless CTS mode is enabled
• Supports flow control using sliding window protocol
• Provides configurable frame length for data frame with variable payload sizes of 32, 64,
96, 128, 256 or 288 bits
• Provides configurable frame length for unsolicited frame with variable payload sizes of
8, 32, 64, 96, 128, 256 or 288 bits
• Supports PLL configuration (such as feedback loop divider) through registers
• Supports LVDS configuration through registers
• Supports multiple loopback modes for checking the physical interface
• Supports automatic ping response generation in slave mode
• Supports for detection of unsupported channel number and unsupported payload size
51.6 Memory map and register definition
All registers are 32-bit wide.
51.6.1 Memory map
Table 972. LFAST memory map
Offset from
LFAST_BASE
(hex)
0000
0004
0008
000C
0010
0014
0018
001C
0020
0024–0028
Register Access
Reset Value
(hex)
Location
LFAST Mode Configuration Register (MCR)
LFAST Speed Control Register (SCR)
LFAST Correlator Control Register (COCR)
LFAST Test Mode Control Register (TMCR)
LFAST Auto Loopback Control Register (ALCR)
R/W 0x0000_0010
Section 51.6.2.1
R/W 0x0001_0000
Section 51.6.2.2
R/W 0x0000_000E
Section 51.6.2.3
R/W 0x0000_0000
Section 51.6.2.4
R/W 0x0000_0000
Section 51.6.2.5
LFAST Rate Change Delay Control Register
(RCDCR)
LFAST Wakeup Delay Control Register (SLCR)
LFAST ICLC Control Register (ICR)
LFAST Ping Control Register (PICR)
Reserved
R/W 0x000F_0000
Section 51.6.2.6
R/W 0x1201_5F02
Section 51.6.2.7
R/W 0x0000_0000
Section 51.6.2.8
R/W 0x0000_80CA
Section 51.6.2.9
1768/4101
RM0421 Rev 5
RM0421 LVDS Fast Asynchronous Serial Transmission – Interprocessor Communications
Table 972. LFAST memory map (continued)
006C–007C
0080
0084
0088–0090
0094
0098
009C
00A0
00A4
00A8
00AC
00B0
Offset from
LFAST_BASE
(hex)
002C
0030
0034
0038
003C
0040
0044
0048
004C
0050
0054
0058
005C
0060
0064
0068
Register Access
Reset Value
(hex)
Location
LFAST Rx FIFO CTS Control Register (RFCR)
LFAST Tx Interrupt Enable Register (TIER)
LFAST Rx Interrupt Enable Register (RIER)
LFAST Rx ICLC Interrupt Enable Register (RIIER)
LFAST PLL Control Register (PLLCR)
LFAST LVDS Control Register (LCR)
LFAST Unsolicited Tx Control Register (UNSTCR)
LFAST Unsolicited Tx Data Registers 8
(UNSTDR8)
LFAST Unsolicited Tx Data Registers 7
(UNSTDR7)
LFAST Unsolicited Tx Data Registers 6
(UNSTDR6)
R/W 0x000F_0009
Section 51.6.2.10
R/W 0x0000_0000
Section 51.6.2.11
R/W 0x0000_0000
Section 51.6.2.12
R/W 0x0000_0000
Section 51.6.2.13
R/W 0x0000_005C
Section 51.6.2.14
R/W 0x0000_5024
Section 51.6.2.15
R/W 0x0000_0000
Section 51.6.2.16
R/W 0x0000_0000
Section 51.6.2.17
R/W 0x0000_0000
Section 51.6.2.17
R/W 0x0000_0000
Section 51.6.2.17
LFAST Unsolicited Tx Data Registers 5
(UNSTDR5)
LFAST Unsolicited Tx Data Registers 4
(UNSTDR4)
LFAST Unsolicited Tx Data Registers 3
(UNSTDR3)
LFAST Unsolicited Tx Data Registers 2
(UNSTDR2)
LFAST Unsolicited Tx Data Registers 1
(UNSTDR1)
LFAST Unsolicited Tx Data Registers 0
(UNSTDR0)
LFAST Unsolicited Rx Status Register (UNSRSR)
LFAST Unsolicited Rx Data Register 8 (UNSRDR8)
LFAST Unsolicited Rx Data Register 7 (UNSRDR7)
R/W
R/W
R/W
R/W
R/W
R/W
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
Section 51.6.2.17
Section 51.6.2.17
Section 51.6.2.17
Section 51.6.2.17
Section 51.6.2.17
Section 51.6.2.17
Reserved
LFAST Global Status Register (GSR)
LFAST Ping Status Register (PISR)
R
R
0x8000_0000
Section 51.6.2.18
0x0000_0000
Section 51.6.2.19
LFAST Data Frame Status Register (DFSR)
Reserved
LFAST Tx Interrupt Status Register (TISR)
R 0x0000_0000
Section 51.6.2.20
R/W 0x0000_0000
Section 51.6.2.21
LFAST Rx Interrupt Status Register (RISR)
LFAST Rx ICLC Interrupt Status Register (RIISR)
LFAST PLL and LVDS Status Register (PLLLSR)
R/W 0x0000_0000
Section 51.6.2.22
R/W 0x0000_0000
Section 51.6.2.23
R 0x0002_0003
Section 51.6.2.24
R/W 0x0000_0000
Section 51.6.2.25
R
R
0x0000 _ 0000
Section 51.6.2.26
0x0000
_
0000
Section 51.6.2.26
RM0421 Rev 5
1769/4101
1839
