RM0421 FlexRay communication controller (FlexRay)
Figure 1332. Physical message buffer structure
SADR_MBDF
Frame Data
Message Buffer Data Field
SADR_MBHF
Frame Header
Message Buffer Header Field
Slot Status
53.6.2.1 Message buffer header field
The message buffer header field is a contiguous region in the FlexRay memory area that occupies eight bytes. It contains the frame header and the slot status. Its structure is shown
in Figure 1332
. The physical start address SADR_MBHF of the message buffer header field must be 16-bit aligned.
53.6.2.1.1 Frame header
The frame header occupies the first six bytes in the message buffer header field. It contains all FlexRay frame header-related information according to the FlexRay Communications
System Protocol Specification, Version 2.1 Rev A . A detailed description of the usage and
the content of the frame header is provided in Section 53.6.5.2.1: Frame header description .
53.6.2.1.2 Slot status
The slot status occupies the last 2 bytes of the message buffer header field. It provides the slot and frame status-related information according to the FlexRay Communications System
Protocol Specification, Version 2.1 Rev A . A detailed description of the content and usage of the slot status is provided in
Section 53.6.5.2.2: Slot status description .
53.6.2.2 Message buffer data field
The message buffer data field is a contiguous area of 2-byte entities. This field contains the frame payload data, or a part of it, of the frame to be transmitted to or received from the
FlexRay bus. The minimum length of this field depends on the specific message buffer
configuration and is specified in the message buffer descriptions given in Section 53.6.3:
Message buffer types
.
53.6.3 Message buffer types
The CC provides three different types of message buffers.
• Individual Message Buffers
• Receive Shadow Buffers
• Receive FIFO Buffers
For each message buffer type, the structure of the physical message buffer is identical. The message buffer types differ only in the structure and content of message buffer control data, which control the related physical message buffer. The message buffer control data are described in the following sections.
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53.6.3.1 Individual message buffers
The individual message buffers are used for all types of frame transmission and for dedicated frame reception based on individual filter settings for each message buffer. The
CC supports three types of individual message buffers, which are described in
Section 53.6.6: Individual message buffer functional description .
Each individual message buffer consists of two parts, the physical message buffer, which is located in the FlexRay memory area, and the message buffer control data, which are located in dedicated registers. The structure of an individual message buffer is given in
Figure 1333 .
Each individual message buffer has a message buffer number n assigned, which determines the set of message buffer control registers associated to this individual message buffer. The individual message buffer with message buffer number n is controlled by the registers FR_MBCCSR n , FR_MBCCFR n , FR_MBFIDR n and FR_MBIDXR n .
The connection between the message buffer control registers and the physical message buffer is established by the message buffer index field, MBIDX, in the Message Buffer Index
Registers (FR_MBIDXRn). The start address SADR_MBHF of the related message buffer header field in the FlexRay memory area is determined according to
Equation 37 .
Equation 37 SADR_MBHF = (FR_MBIDXR n [MBIDX] × 8) + SMBA
The data field belonging to a particular physical message buffer is characterized by the data field offset. For each physical message buffer with MBIDX i, the FR_MBDORi contains the offset of the corresponding message buffer data field with respect to the CC FlexRay memory area base address as provided by SMBA field in the System Memory Base
Address Register (FR_SYMBADR).
The data field offset is used to determine the start address SADR_MBDF of the
corresponding message buffer data field in the FlexRay memory area according to Equation
38 .
Equation 38 SADR_MBDF = [Data Field Offset] + SMBA
The FR_MBDOR n are stored in the module internal memory LRAM. Refer to
Section 53.7.2.3: CHI LRAM initialization for the setup of the data field offset values.
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Figure 1333. Individual message buffer structure
(min) MBDSR[MBSEG1DS]
×
2 bytes / MBDSR[MBSEG2DS]
×
2 bytes
SADR_MBDF
Frame Data
Message Buffer Data Field
SADR_MBHF
Frame Header
Message Buffer Header Field
Slot Status
FR_MBCCSRn FR_MBCCFRn FR_MBFIDRn
Message Buffer Control Registers
FR_MBIDXRn
FR_MBDOR131
…
FR_MBDORi
…
FR_MBDOR0
53.6.3.1.1 Individual message buffer segments
The set of the individual message buffers can be split up into two message buffer segments using the Message Buffer Segment Size and Utilization Register (FR_MBSSUTR). All individual message buffers with a message buffer number n ≤
FR_MBSSUTR[LAST_MB_SEG1] belong to the first message buffer segment. All individual message buffers with a message buffer number n > FR_MBSSUTR[LAST_MB_SEG1] belong to the second message buffer segment. The following rules apply to the length of the message buffer data field:
• All physical message buffers associated to individual message buffers that belong to the same message buffer segment must have message buffer data fields of the same length.
• The minimum length of the message buffer data field for individual message buffers in the first message buffer segment is 2 × FR_MBDSR[MBSEG1DS] bytes.
• The minimum length of the message buffer data field for individual message buffers assigned to the second segment is 2 × FR_MBDSR[MBSEG2DS] bytes.
53.6.3.2 Receive shadow buffers
The receive shadow buffers are required for the individual message buffers’ frame reception process. The CC provides four receive shadow buffers: one receive shadow buffer per channel and per message buffer segment.
Each receive shadow buffer consists of two parts: the physical message buffer located in the FlexRay memory area and the receive shadow buffer control registers located in
dedicated registers. The structure of a receive shadow buffer is shown in Figure 1334
. The four internal shadow buffer control registers can be accessed by the Receive Shadow Buffer
Index Register (FR_RSBIR).
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The connection between the receive shadow buffer control register and the physical message buffer for the selected receive shadow buffer is established by the receive shadow buffer index field RSBIDX in the Receive Shadow Buffer Index Register (FR_RSBIR). The start address SADR_MBHF of the related message buffer header field in the FlexRay
memory area is determined according to Equation 39
.
Equation 39 SADR_MBHF = (FR_RSBIR[RSBIDX] × 8) + SMBA
The length required for the message buffer data field depends on the message buffer segment that the receive shadow buffer is assigned to. For the receive shadow buffers assigned to the first message buffer segment, the length must be the same as for the individual message buffers assigned to the first message buffer segment. For the receive shadow buffers assigned to the second message buffer segment, the length must be the same as for the individual message buffers assigned to the second message buffer segment. The receive shadow buffer assignment is described in Receive Shadow Buffer
Index Register (FR_RSBIR).
Figure 1334. Receive shadow buffer structure
(min) MBDSR[MBSEG1DS]
×
2 bytes / MBDSR[MBSEG2DS]
×
2 bytes
SADR_MBDF
Frame Data
Message Buffer Data Field
SADR_MBHF
Frame Header
Message Buffer Header Field
Slot Status
RSBIDX[0]
RSBIDX[1]
RSBIDX[2]
RSBIDX[3]
Receive Shadow Buffer Control Register
FR_MBDOR131
…
FR_MBDORi
…
FR_MBDOR0
53.6.3.3 Receive FIFO
The receive FIFO implements a frame reception system based on the FIFO concept. The
CC provides two independent receive FIFOs, one per channel.
A receive FIFO consists of a set of physical message buffers in the FlexRay memory area and a set of receive FIFO control registers located in dedicated registers. The structure of a receive FIFO is given in
Figure 1335 .
The connection between the receive FIFO control registers and the set of physical message buffers is established by the Receive FIFO Start Index Register (FR_RFSIR), the Receive
FIFO Depth and Size Register (FR_RFDSR), and the Receive FIFO A Read Index Register
(FR_RFARIR)/Receive FIFO B Read Index Register (FR_RFBRIR).
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The system memory base address SMBA valid for the receive FIFOs is defined by the system memory base address register selected by the FIFO address mode bit
FR_MCR[FAM], refer to
Section 53.5.2.4: Module Configuration Register (FR_MCR)
.
The start byte address SADR_MBHF[1] of the first message buffer header field that belongs
to the receive FIFO is determined according to Equation 40
.
Equation 40 SADR_MBHF[1] = (8 × FR_RFSIR[SIDX]) + SMBA
The start byte address SADR_MBHF[n] of the last message buffer header field that belongs to the receive FIFO in the FlexRay memory area is determined according to
Equation 41 .
Equation 41 SADR_MBHF[n] =
(8 × (FR_RFSIR[SIDX] + FR_RFDSR[FIFO_DEPTH])) + SMBA
The required information to access the current entry of the FIFO is given in the following registers:
• The registers Receive FIFO A Read Index Register (FR_RFARIR) and Receive FIFO B
Read Index Register (FR_RFBRIR) provide the index of the physical message buffer belonging to the current entry.
• The data field offset belonging to the current FIFO entry RF_DFO[X] must be calculated using the current read index i according to the following formula:
Equation 42 RF_DFO[X] =
FR_RFSDOR[X] + (FR_RFDSR[X][ENTRY_SIZE] × 2) × (i - R_RFSIR[SIDX])
The current read index loops up starting at the number given in the FR_RD[A/B]RDIDX register for the required number of entries.
Refer to Section 53.6.9.8: FIFO update
for details about updating the FIFO read pointer.
All message buffer header fields assigned to a receive FIFO are within a contiguous region defined by FR_RFSIR[SIDX] and FR_RFDSR[FIFO_DEPTH].
The data sections of all FIFO entries within on receive FIFO are of the same length defined by FR_RFDSR[FIFO_SIZE].
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+
+
Figure 1335. Receive FIFO structure
(min) RFDSR[ENTRY_SIZE] ×
2 bytes
SADR_MBDF[n]
Frame Data[n]
SADR_MBDF[i]
Frame Data[i]
SADR_MBDF[1]
SADR_MBHF[n]
Frame Header[n]
SADR_MBHF[i]
Frame Data[1]
Message Buffer Data Fields
Slot Status[n]
Frame Header[i] Slot Status[i]
SADR_MBHF[1]
Frame Header[1]
Message Buffer Header Fields
Slot Status[1]
RM0421
RF_DFO[A]
RF_DFO[B]
RFDSR[A]
RFDSR[B]
RFSIR[A]
RFSIR[B]
RFARIR
RFBRIR
Receive FIFO Control Register
Note: The actual values of the data field offsets RF_DFO[A/B] need to be calculated according to
Equation 42 . They are not stored in a register.
53.6.3.4 Message buffer configuration and control data
This section describes the configuration and control data for each message buffer type.
53.6.3.4.1 Individual message buffer configuration data
Before an individual message buffer can be used for transmission or reception, it must be configured. There is a set of common configuration parameters that applies to all individual message buffers and a set of configuration parameters that applies to each message buffer individually.
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53.6.3.4.2 Common configuration data
The set of common configuration data for individual message buffers is located in the following registers:
• Message Buffer Data Size Register (FR_MBDSR)
The MBSEG2DS and MBSEG1DS fields define the minimum length of the message buffer data field with respect to the message buffer segment.
• Message Buffer Segment Size and Utilization Register (FR_MBSSUTR)
The LAST_MB_SEG1 and LAST_MB_UTIL fields define the segmentation of the individual message buffers and the number of individual message buffers that are
used. For more details, refer to Section 53.6.3.1.1: Individual message buffer segments .
53.6.3.4.3 Specific configuration data
The set of message buffer specific configuration data for individual message buffers is located in the following registers:
• Message Buffer Configuration, Control, Status Registers (FR_MBCCSRn)
The MTD bit configures the message buffer type.
• Message Buffer Cycle Counter Filter Registers (FR_MBCCFRn)
The MTM, CHA, CHB bits configure the transmission mode and the channel assignment. The CCFE, CCFMSK, and CCFVAL bits and fields configure the cycle counter filter.
• Message Buffer Frame ID Registers (FR_MBFIDRn)
For a transmit message buffer, the FID field is used to determine the slot in which the message in this message buffer will be transmitted.
• Message Buffer Index Registers (FR_MBIDXRn)
This MBIDX field provides the index of the message buffer header field of the physical message buffer that is currently associated with this message buffer.
53.6.3.5 Individual message buffer control data
During normal operation, each individual message buffer can be controlled by the CMT,
LCKT, EDT, and MBIE control and trigger bits in the Message Buffer Configuration, Control,
Status Registers (FR_MBCCSRn).
53.6.3.6 Receive shadow buffer configuration data
Before the individual message buffers can receive frames, the receive shadow buffers must be configured. The configuration data are provided by the Receive Shadow Buffer Index
Register (FR_RSBIR). For each receive shadow buffer, the application provides the message buffer header index. When the protocol is in the POC:normal active or
POC:normal passive state, the receive shadow buffers are under full CC control.
53.6.3.7 Receive FIFO control and configuration data
This section describes the configuration and control data for the two receive FIFOs.
53.6.3.7.1 Receive FIFO configuration data
The CC provides two functional independent receive FIFOs, one per channel. The FIFOs have a common subset of configuration data:
• Receive FIFO Periodic Timer Register (FR_RFPTR)
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