Input clock frequency. STMicroelectronics SPC58xNx 32-bit Power Architecture microcontroller, SPC58NN84C3, SPC58NN84E7

RM0421 Dual PLL digital interface (PLLDIG)

26.6.1 Input clock frequency

PLL0 and PLL1 are designed to operate over an input clock frequency range. The operating ranges for each PLL are discussed in detail in the SPC58xNx datasheet .

26.6.2 Clock configuration

The relationship between input and output frequency is determined by programming the

PLL0DV, PLL1DV and PLL1FD registers, and calculated according to the following equations:

Equation 4

×

PLL0DV MFD

]

PLL0DV PREDIV

]

PLL0DV RFDPHI

]

Equation 5

×

×

[ ]

]

PLL0DV RFDPHI1

]

Note:

Equation 6

×









] + -----------------------------------------------------

]

2

[

12

] 







Depending on DTHDIS value the multiplication factor of

Equation 6

can change as described in PLL1DV[DTHDIS] field description (refer to

Table 347

).

The relationship between the VCO frequency f

VCO

and the output frequency of the PLLs is determined by the configuration of the PLL0DV, PLL1DV and PLL1FD registers, according to the following equations:

Equation 7

fpll0_VCO

=

×

PLL0DV PREDIV

]

] ×

2

Equation 8

= × ] + -----------------------------------------------------

]

2

[

12



RM0421 Rev 5

695/4101

699