RM0421 Self-Test Control Unit (STCU2)
• STCU2 Load Shifter FSM: This module includes the common shifter register and the respective state machine used to program the LBIST or MBIST registers and read back the data to be checked at the end of each self-test operation.
• LBIST interface : This module includes the interface between the LBIST engines and the STCU2 controllers of the device.
• MBIST interface : This module includes the interface between the MBIST controller and STCU2 controllers.
84.3.1 IPS bus interface
The IPS bus interface is a slave bus used for configuration purposes via CPU. The following bus read operations (contiguous byte enables) are supported:
• Word (32 bits) data read operations to any registers.
• Low and high half-words (16 bits, data[31:16] or data[15:0]) data read operations to any registers.
• Byte (8 bits, data[31:24] or data[23:16] or data[15:8] or data[7:0]) data read operations to any registers.
• Any other operation (free byte enables or other operations) has to be avoided.
The same operations are also supported in write mode under the following circumstances:
• The self-test sequence parameters are loaded before offline self-test is executed.
• The IPS access on some specific registers (see
Section 84.5: Register description ) is
allowed by software only when the bit STCU_CFG[WRP] is cleared.
• Write operations are not supported and all STCU2 registers can only be read in all other circumstances except for the following R/W bits: STCU_CFG[WRP],
STCU_ERR_STAT[UFSF] and STCU_ERR_STAT[RFSF]. See the respective register descriptions for additional details.
The STCU2 module generates a transfer error in the following cases:
• Any write/read access to the register addresses not mapped on the peripheral but included in the address space of the peripheral.
• Any write/read operation different from byte/halfword/word (free byte enables or other operations) on each register.
• Any write operation on double security key register applying a wrong sequence of keys
(the two write operations cannot be interleaved with other accesses to STCU2 registers).
• Any write operation performed on a register when the double security keys have not been applied.
• Any write operation performed on registers when the STCU_CFG[WRP] bit is set and the access is performed through software (IPS interface).
• Any write operation performed through software (IPS interface) on row registers.
• Any write operation performed offline on registers where writes are only allowed during the online self-test phase when STCU_CFG[WRP] = 1.
• Any write operation performed on read only registers.
The registers of the STCU2 module are accessible (read/write) in each access mode: user, supervisor or test.
A transfer error is not generated for write operations to bits marked Reserved .
RM0421 Rev 5
3705/4101
3760
