RM0421 ASC Modeling Unit version 2 (AMU2) corresponding pointer and parameter registers. Once the data load and register initialization are completed, the calculation is started by writing the AMU2_CCR{1,2}CH n registers. In this case, the AMU completion and error indicators are configured to generate interrupts to the processor; the calculation actually begins when the AMU2_CCR2CH n [S1SRT, S23SRT] bits are set.
The AMU2 performs the calculation and then typically generates an interrupt, signaling successful completion or some type of error termination or an N crossing debug event.
As the processor handles the interrupt, the 64-bit double precision result
(AMU2_RES64{M,L}CH n ) is retrieved along with the status flags in the AMU2_SEIRCH n register. After processing the interrupt, the service routine clears the interrupt source by writing a “1” to clear the appropriate flag in the low-order byte of the AMU2_SEIRCH n register. The processor then performs any required analysis of the status indicators before saving the result.
The preceding description assumes the processor is interrupted when the AMU2 completes as this would be the typical scenario. The AMU2 also provides a channel busy flag
(AMU2_SEIRCH n [CHBSY]) that the processor can poll to determine whether the calculation is finished.
88.4.2 Single calculation using SDMA for data load, CPU for post-processing
In this example, it is assumed the processor has created the appropriate data structure in system Flash memory so that the System DMA can perform the data load into the ARAM plus the initialization of the pointer and parameter registers.
The SDMA would typically require two separate TCDs (Transfer Control Descriptors): one to perform the data move from system Flash into the ARAM, and a second to load the programming model registers. The SDMA can use the scatter/gather feature to process the two TCDs in a single channel, or 2 channels can be used where the first channel performing the data move “links” to the second channel performing the register loads. In any case, the second data transfer loads the programming model using an 80-byte block transfer. Using
CH0 as an example, this block data transfer writes from the AMU2_P1PTRCH n register
(offset address 0x1_0010) to the AMU2_CCR2CH n registers (offset address 0x1_005c) before beginning the actual calculation.
It should be noted the programming model of the AMU2 is organized such that an optimized
80-byte burst transfer (5 x 8-byte 8-beat bursts) can be used to load the registers. The optimized block transfer does not include the AMU2_NCH n register for two reasons:
1.
The use of the N crossing functionality is a debug feature and not intended for normal system operation;
2. The inclusion of the AMU2_NCH n functionality must be properly enabled by setting
AMU2_CCR2CH n [ENCRS] = 1. Stated differently, the AMU2_NCH n functionality is completely disabled if AMU2_CCR2CH n [ENCRS] = 0. In the optimized block transfer, the AMU2_NCH n register does not need to be initialized, and AMU2_CCR2CH n register (with ENCRS = 0) is always the last register written.
Note, the AMU2_NCH n register can be included in the sequential data transfer for the register writes by increasing the total number of bytes to be transferred to 84 and using 32bit writes.
RM0421 Rev 5
3899/4101
3905
ASC Modeling Unit version 2 (AMU2) RM0421
As before, the AMU completion and error indicators are configured to generate interrupts to the processor; the calculation actually begins when the AMU2_CCR2CH n [S1SRT, S23SRT] bits are set by the SDMA’s last transfer.
The channel performs the calculation and generates an interrupt, signaling a successful completion or some type of error termination or an N crossing debug event.
As the processor handles the interrupt, the 64-bit double precision result
(AMU2_RES64{M,L}CH n ) is retrieved along with the status flags in the AMU2_SEIRCH n register. After processing the interrupt, the service routine clears the interrupt source by writing a “1” to clear the appropriate flag in the low-order byte of the AMU2_SEIRCH n register. The processor then performs any required analysis of the status indicators before saving the result.
88.4.3 Single calculation using SDMA + ADMA for data load, CPU for post-processing
For this case, it is assumed the processor has created the appropriate data structure in system Flash memory so that the System DMA and the ADMA collectively can perform the data load into the ARAM plus the initialization of the pointer and parameter registers.
In this example, let the ADMA move the U[*] vector into the ARAM and the SDMA move all the rest of the data.
The SDMA would typically require two separate TCDs (Transfer Control Descriptors): one to perform the data move from system Flash into the ARAM, and a second to load the programming model registers. The SDMA can use the scatter/gather feature to process the two TCDs in a single channel, or 2 channels can be used where the first channel performing the data move “links” to the second channel performing the register load. The second data transfer loads the programming model using an 80-byte (5 x 16 byte 4-beat bursts) block transfer. Using CH0 as an example, this block data transfer writes from the
AMU2_P1PTRCH n register (offset address 0x1_0010) to the AMU2_CCR2CH n registers
(offset address 0x1_005c) before beginning the actual calculation. In this example, the programming model initialization configures the ADMA to move the U[*] vector into the
ARAM and the AMU2_CCR2CH n [WFDS1, WFDS23] conditional start bits are set (and
[S1SRT, S23SRT] cleared) to signal the start of the calculation engine is dependent on the completion of the ADMA.
As before, the AMU completion and error indicators are configured to generate interrupts to the processor; the calculation actually begins when the ADMA completes the data transfer of the U[*] vector into the ARAM.
The channel performs the calculation and generates an interrupt, signaling a successful completion or some type of error termination or an N crossing debug event.
As the processor handles the interrupt, the 64-bit double precision result
(AMU2_RES64{M,L}CH n ) is retrieved along with the status flags in the AMU2_SEIRCH n register. After processing the interrupt, the service routine clears the interrupt source by writing a “1” to clear the appropriate flag in the low-order byte of the AMU2_SEIRCH n register. The processor then performs any required analysis of the status indicators before saving the result.
3900/4101
RM0421 Rev 5
