LVDS Fast Asynchronous Serial Transmission – High Speed Debug RM0421
75.5 Features
• Supports slave only mode
• Supports asynchronous data transfer rates up to the maximum data rated shown in the product Datasheet
• Transmits and receives data and unsolicited frames
• Receives ICLC frames
• Supports processor controlled transfer of ICLC frame with 8-bit payload size to implement the data rate changes and test modes
• Supports flow control using sliding window protocol
• Provides transmit of data frame length with 96 bits of payload size and reception of data frame with 128 bits of payload size
• Provides configurable frame length for unsolicited frame with variable payload sizes of
8, 32, 64, 96, 128, 256 or 288 bits
• Supports PLL configuration (such as feedback loop divider) through registers
• Supports LVDS configuration through registers
• Supports multiple loopback modes for checking the physical interface
• Supports automatic ping response generation
• Supports for detection of unsupported channel number and unsupported payload size
75.6 Memory map and register definition
All registers are 32-bit wide.
75.6.1 Memory map
Table 1943. LFAST memory map
Offset from
LFAST_BASE
(hex)
0000
0004
0008
000C
0010
0014
0018
001C
0020
0024–002C
0030–0038
Register Access
Reset Value
(hex)
Location
LFAST Mode Configuration Register (MCR)
LFAST Speed Control Register (SCR)
LFAST Correlator Control Register (COCR)
LFAST Test Mode Control Register (TMCR)
LFAST Auto Loopback Control Register (ALCR)
LFAST Rate Change Delay Control Register
(RCDCR)
LFAST Wakeup Delay Control Register (SLCR)
R/W
R/W
R/W
R/W
R/W
R/W
0x0000_0010
0x0001_0000
0x0000_000E
0x0000_0000
0x0000_0000
0x000F_0000
Section 75.6.2.1
Section 75.6.2.2
Section 75.6.2.3
Section 75.6.2.4
Section 75.6.2.5
Section 75.6.2.6
R/W 0x1201_5F02
Section 75.6.2.7
Reserved
LFAST Ping Control Register (PICR) R/W 0x0000_80CA
Section 75.6.2.8
Reserved
Reserved – Access will not generate errors
3394/4101
RM0421 Rev 5
RM0421 LVDS Fast Asynchronous Serial Transmission – High Speed Debug
Table 1943. LFAST memory map (continued)
006C–007C
0080
0084–0090
0094
0098
009C
00A0
00A4
00A8
00AC
00B0
00B4
00B8
00BC
00C0
00C4
Offset from
LFAST_BASE
(hex)
003C
0040
0044
0048
004C
0050
0054
0058
005C
0060
0064
0068
Register Access
Reset Value
(hex)
Location
Reserved
LFAST LVDS Control Register (LCR)
LFAST Unsolicited Tx Control Register (UNSTCR)
LFAST Unsolicited Tx Data Registers 8
(UNSTDR8)
LFAST Unsolicited Tx Data Registers 7
(UNSTDR7)
LFAST Unsolicited Tx Data Registers 6
(UNSTDR6)
LFAST Unsolicited Tx Data Registers 5
(UNSTDR5)
LFAST Unsolicited Tx Data Registers 4
(UNSTDR4)
R/W 0x0000_5024
Section 75.6.2.9
R/W 0x0000_0000
Section 75.6.2.10
R/W 0x0000_0000
Section 75.6.2.11
R/W 0x0000_0000
Section 75.6.2.11
R/W 0x0000_0000
Section 75.6.2.11
R/W 0x0000_0000
Section 75.6.2.11
R/W 0x0000_0000
Section 75.6.2.11
LFAST Unsolicited Tx Data Registers 3
(UNSTDR3)
LFAST Unsolicited Tx Data Registers 2
(UNSTDR2)
LFAST Unsolicited Tx Data Registers 1
(UNSTDR1)
LFAST Unsolicited Tx Data Registers 0
(UNSTDR0)
R/W
R/W
R/W
R/W
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
Section 75.6.2.11
Section 75.6.2.11
Section 75.6.2.11
Section 75.6.2.11
Reserved
LFAST Global Status Register (GSR) R 0x0000_0000
Section 75.6.2.12
Reserved
LFAST Data Frame Status Register (DFSR)
LFAST Tx Interrupt Status Register (TISR)
LFAST Rx Interrupt Status Register (RISR)
LFAST Rx ICLC Interrupt Status Register (RIISR)
R 0x0000_0000
Section 75.6.2.13
R/W 0x0000_0000
Section 75.6.2.14
R/W 0x0000_0000
Section 75.6.2.15
R/W 0x0000_0000
Section 75.6.2.16
LFAST PLL and LVDS Status Register (PLLLSR)
LFAST Unsolicited Rx Status Register (UNSRSR)
LFAST Unsolicited Rx Data Register 8 (UNSRDR8)
LFAST Unsolicited Rx Data Register 7 (UNSRDR7)
LFAST Unsolicited Rx Data Register 6 (UNSRDR6)
LFAST Unsolicited Rx Data Register 5 (UNSRDR5)
LFAST Unsolicited Rx Data Register 4 (UNSRDR4)
LFAST Unsolicited Rx Data Register 3 (UNSRDR3)
LFAST Unsolicited Rx Data Register 2 (UNSRDR2)
R 0x0002_0003
Section 75.6.2.17
R/W 0x0000_0000
Section 75.6.2.18
R
R
R
R
R
R
R
0x0000
_
0000
Section 75.6.2.19
0x0000
_
0000
Section 75.6.2.19
0x0000
_
0000
Section 75.6.2.19
0x0000 _ 0000
Section 75.6.2.19
0x0000
_
0000
Section 75.6.2.19
0x0000 _ 0000
Section 75.6.2.19
0x0000
_
0000
Section 75.6.2.19
RM0421 Rev 5
3395/4101
3448
